# Error in simulating bdf with Waveform.vwf.vht, but bdf compiles successfully

I am trying to design an instruction register and controller for an ALU that I designed previously. I made the register with 2 muxes and 2 D flip-flops, and I made the controller with a T flip-flop and a part I programmed in VHDL. Both the BDF and the VHDL file compile successfully; however, when I try to run a simulation with Quartus's University Program VWF, I always get errors that prevent the simulation. I've run a lot of simulations for other projects, and I've never had this issue before. Any help would be appreciated. Here's my VHDL code:

    library ieee; use ieee.std_logic_1164.all;
entity Controller is port(
S: in std_logic;
IR: in std_logic_vector (1 downto 0);
IR_LD: out std_logic;
MSA: out std_logic_vector (1 downto 0);
MSB: out std_logic_vector (1 downto 0);
MSC: out std_logic_vector (2 downto 0)
);
end Controller;
architecture behavior of Controller is
begin
IR_LD <=
(NOT S);
MSC(2) <=
(S AND IR(1));
MSC(1) <=
(S AND IR(1) AND IR(0));
MSC(0) <=
(S AND IR(1));
MSB(1) <=
((NOT S) OR IR(1) OR IR(0));
MSB(0) <=
(S AND (NOT IR(1)) AND (NOT IR(0)));
MSA(1) <=
(S AND IR(1));
MSA(0) <=
((NOT S) OR IR(1) OR (NOT IR(0)));
end behavior;


Here are screenshots of my BDF:

Here's a screenshot of the vwf file:

And here's a screenshot of the part of the Simulation Flow Progress report where the errors occur: