Error in simulating bdf with Waveform.vwf.vht, but bdf compiles successfully

Question

I am trying to design an instruction register and controller for an ALU that I designed previously. I made the register with 2 muxes and 2 D flip-flops, and I made the controller with a T flip-flop and a part I programmed in VHDL. Both the BDF and the VHDL file compile successfully; however, when I try to run a simulation with Quartus's University Program VWF, I always get errors that prevent the simulation. I've run a lot of simulations for other projects, and I've never had this issue before. Any help would be appreciated. Here's my VHDL code:

    library ieee; use ieee.std_logic_1164.all;
    entity Controller is port(  
        S: in std_logic;
        IR: in std_logic_vector (1 downto 0);
        IR_LD: out std_logic;
        MSA: out std_logic_vector (1 downto 0);
        MSB: out std_logic_vector (1 downto 0);
        MSC: out std_logic_vector (2 downto 0)
    );
    end Controller;
    architecture behavior of Controller is
    begin
        IR_LD <= 
                (NOT S);
        MSC(2) <=
                (S AND IR(1));
        MSC(1) <=
                (S AND IR(1) AND IR(0));
        MSC(0) <=
                (S AND IR(1));
        MSB(1) <=
                ((NOT S) OR IR(1) OR IR(0));
        MSB(0) <=
                (S AND (NOT IR(1)) AND (NOT IR(0))); 
        MSA(1) <=
                (S AND IR(1));
        MSA(0) <=
                ((NOT S) OR IR(1) OR (NOT IR(0)));
    end behavior;

Here are screenshots of my BDF:

Here's a screenshot of the vwf file:

And here's a screenshot of the part of the Simulation Flow Progress report where the errors occur:

The errors read as follows:

** Error: Waveform.vwf.vht(39): near "In": (vcom-1576) expecting IDENTIFIER.

** Error: Waveform.vwf.vht(41): near "Out": (vcom-1576) expecting IDENTIFIER.

** Error: Waveform.vwf.vht(63): near "In": syntax error

** Error: Waveform.vwf.vht(71): Statement cannot be labeled.

** Error: Waveform.vwf.vht(89): near "t_prcs_": Identifier may not end with >an underline.

** Error: Waveform.vwf.vht(89): near "\In\": (vcom-1576) expecting == or '+' >or '-' or '&'.

** Error: Waveform.vwf.vht(89): near "3:": (vcom-111) No digits found in >mantissa part of based literal.

** Error: Waveform.vwf.vht(89): near "3: ": (vcom-113) Mantissa part of based >integer literal terminates with ' '; should be ':'.

** Error: Waveform.vwf.vht(92): Illegal concurrent statement.

** Error: Waveform.vwf.vht(93): near "In": syntax error

** Error: Waveform.vwf.vht(94): Illegal concurrent statement.

** Error: Waveform.vwf.vht(95): near "In": syntax error

** Error: Waveform.vwf.vht(96): Illegal concurrent statement.

** Error: Waveform.vwf.vht(97): near "PROCESS": (vcom-1576) expecting ';'.

End time: 19:21:31 on Jul 23,2019, Elapsed time: 0:00:00

Errors: 14, Warnings: 0

** Error: c:/intelfpga_lite/18.1/modelsim_ase/win32aloem/vcom failed.

Executing ONERROR command at macro ./LAB6_Part1.do line 4

Answer 1

I changed the input In[3..0] to Input[3..0] and the output Out[3..0] to Output[3..0] and I was able to successfully simulate the project.