I am implementing an AXI4-Lite slave interface in FPGA and I want to have the read/write operations to complete in as few clock cycles as possible. With that in mind, can I assume any specific relationship between AWVALID and WVALID coming from the master? Such as AWVALID and WVALID will always be asserted together or one would come certain number of clock cycles after the other?

PS: The master interface I'm working with is the Xilinx DMA/Bridge Subsystem for PCIe.


AWVALID and WVALID have no specific timing relationship to each other.

AWVALID is asserted at the beginning of a transfer to qualify the address and other AW bus info.

WVALID is for W bus and only qualifies WDATA/WSTRB/etc. It can be asserted at the same time as AWVALID but you can't count on that.

In any case, you cannot assert BVALID until both AWVALID/AWREADY and WVALID/WREADY have occurred.

That said, if you are looking for higher performance why not just use AXI4, which supports burst transfers and wider bus widths? Especially if you’re using xdma (DMA/Bridge subsystsem, aka. PG195.) AXI4-Lite is designed for ease of use for control registers and such, not for ultimate performance.


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