# Half Bridge with PWM- gate signal problem

After making a half bridge inverter using a square wave (I asked a question on this website about it previously) I have now decided to use PWM signal in order to obtain a sine wave output and have come across some new issues.

Here is the circuit on LTSpice:

The load is an 100u inductor and the PWM is created and input into a gate drive before it is used to drive the MOSFETs.

When I run the simulation, the high side mosfet signal (HO)- linked to the behaviour of Vs- follows the shape of the current in the inductor L1 and does not reach 0V and turn off as it should for much of the time causing the circuit to not work.

If I increase the inductor value and therefore decreased the current in the circuit the problem is fixed. However I am not sure I understand why a high current would cause the voltage to not reach zero.

If I replace the inductor with a resistor as the load then the problem also is fixed suggesting it is due to the behaviour of the current due to the inductive load?

Here are the waveforms from the simulation- the second set is the same but zoomed in to better show what is happening.

Can anyone explain what is causing this or what I need to change in order to fix this circuit?

## 1 Answer

You are correct: it is the inductive current causing your problem.

You can see from your simulation output that the voltage vs is sometimes greater than vrail. During this time, M1 is conducting in the reverse direction through its body diode and back into the supply, regardless of the gate voltage. When you put in a resistive load, the voltage will not exceed the rail, and hence M1 can be controlled by its gate.

Good luck!

• Hi John, I understand your point and seems to make sense as to explaining why I'm having these problems. I have tested with a resistive load and you are correct. However I think I am a bit confused as to how the inductive current causes the voltage at Vs to increase? could you briefly explain this, thanks Jul 26, 2019 at 13:11
• I will try. C1, C3, and L1 form an L-C, or "tank" circuit. Inductors and capacitors have the property of instantaneously storing energy, and so not only are you applying an external excitation, the components are storing and transferring energy back and forth between L1 and C1 and C3. The stored energy plus your excitation means that the tank circuit voltage can exceed the excitation voltage. With an RC circuit, the resistor does not store energy, so the voltage will not exceed the excitation voltage. MOSFETs act like a diode when back biased ("body diode"), regardless of the gate voltage. Jul 26, 2019 at 14:40
• OK yes that makes sense, if I was to estimate the voltage at Vs would I be correct to do Vrail - VL. Where VL would equal L*di/dt. I am not sure about this as from the graphs, when HO is high, the current in the inductor, IL, is decreasing. So VL would be a negative value so Vs becomes larger than Vrail, as we have discussed. Am I correct in saying IL is decreasing when HO is on because the current is flowing through the body diode because Vs is greater than Vrail? If so, what is confusing me is that Vs>Vrail because IL is decreasing, however IL is only decreasing because Vs>Vrail. Jul 30, 2019 at 11:24
• Remember that di/dt is the rate of change of current, and the magnitude of voltage on the inductor will be proportional to this rate of change, regardless of whether the current is increasing or decreasing. Only the polarity of the associated voltage changes. So even if you have a decreasing current, di/dt can be large. It doesn't matter if the current is increasing or decreasing, you will still get a voltage - the magnitude is proportional to how fast the current is decreasing. Jul 31, 2019 at 11:05
• Hi again John, I was wondering out of interest if you know of any solutions to this problem other than using a resistive load? Aug 6, 2019 at 15:32