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This question is a follow-up to Relationship between AWVALID and WVALID in AXI4-Lite interface, from which I learned that AWVALID and WVALID have no specific timing relationship.

Now I have a slightly different question. If AWREADY is asserted in response to AWVALID, is there any guarantee that AWADDR will stay asserted till WREADY, BVALID, or BREADY is asserted?
I'm only asking this because I have seen some codes that look at WVALID alone for completing the write operations. They totally neglect AWVALID and keeps AWREADY=1 at all times, with the assumption that AWADDR will be valid. Is this perfectly fine to do?

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No. When AWREADY is asserted with AWVALID high, AWVALID must be deasserted on the next clock edge, or the other signals must be updated to reflect the next transaction. With AWVALID deasserted, AWADDR can take on any value. You cannot rely on the value of any of the AW* signals after completing the handshake by asserting AWREADY.

A module that assumes differently will then depend on the specific implementation of whatever component is upstream, something which could lead to hard to find bugs and compatibility issues. I also think it is a violation of the spec to do something like that.

You have two options here: either store the value you need and complete the transfer immediately by asserting AWREADY, or hold off on asserting AWREADY until you no longer need the value.

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