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I am trying to understand the negative LDO. I have the following questions regarding that:

  • What is the main difference between positive and negative LDO?
  • Is the reference voltage of LDO connected to the positive terminal or negative terminal of error amplifier?
  • Is there any change in loop behaviour of a negative LDO?
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    \$\begingroup\$ Link to a datasheet (in the question - not in the comments) so we can talk about a particular LDO and pinout. \$\endgroup\$
    – Transistor
    Jul 26, 2019 at 10:14

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There are many different designs for LDOs, true for both positive and negative types. Some reference with respect to ground, some with respect to output. Some have stable loops into any load capacitor, some require a minimum ESR to be stable. The detailed behaviour for any given LDO will be spelled out in the data sheet.

The one guaranteed difference between positive and negative LDOs is the sign of the input and output terminal with respect to ground.

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  • \$\begingroup\$ Not necessarily with respect to ground. I've used negative linear regulators referenced to VCC many times to supply the termination voltage for PECL logic, for example. \$\endgroup\$
    – The Photon
    Jul 26, 2019 at 14:42

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