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let's consider a certain finite state machine, for instance a Mealy Machine:

enter image description here

I was told that it cannot work properly in absence of a reset signal (for the State Register), since we would not know the initial state of the device at the moment in which it is switched on.

But I do not understand clearly this concept. In fact, a Mealy machine may be described by an ASM diagram, for instance this one:

enter image description here

Let's consider the instant in which it is switched on: why cannot it work properly without a reset button?

If it is not present, I think that the machine will follow anyway the related ASM diagram correctly, and the difference is simply that it may start from another state (for instance from s1 instead of s0).

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    \$\begingroup\$ "the difference is simply that it may start from another state" That is true but almost all state-machines have to work according to a sequence where it is not allowed to skip some initial steps. Step1 : Put foot in shoe. Step 2: Tie shoelaces. \$\endgroup\$ – Oldfart Jul 26 at 15:39
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    \$\begingroup\$ Consider a machine of two states: State1 - Wait for enemy missile to be detected and transfer to State2 if detected. State2 - Nuke the enemy. Now... would you care which state the system will start up in? \$\endgroup\$ – Eugene Sh. Jul 26 at 15:42
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    \$\begingroup\$ Many practical state machines have invalid states (due to either incomplete decoding or one-hot encoding) or even store the state in multiple theoretically duplicate registers - think about what happens if those get out of sync. \$\endgroup\$ – Chris Stratton Jul 26 at 15:45
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You need to remember that the FSM needs to be built with actual physical components (even if it is in an FPGA). An FSM needs memory to keep track of the states, most of the time these memory elements are flip-flops. Upon power up, a flip flop can choose one of three states: High, Low or in-between (metastablity which means both transistors are on and it's a really bad state to be in).

The first reason the state machine needs to be reset is to prevent metastablity. Many FPGA's do this with an asyncronus reset.

The second reason is to get the state machine into a pre-determined state. For many applications, having a state machine starting at a random point is unacceptable.

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If you are talking about the simulation of a state machine then this is usually true. Without a reset signal the state register wakes up with an unknown value. The next state logic can do nothing but produce an unknown output from an unknown input, so the machine never reaches a stable state.

For a real, physical state machine the answer will depend a great deal on what the machine is supposed to do. Is it possible to wake up in an undefined state for which there is no transition to a defined state? Is it possible to wake up in a state that would cause the rest of the system to malfunction? Does the system require that the machine transition in an orderly fashion from some initial state? These questions cannot be answered in general.

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