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So, I was trying to create an FSM for my module which supposed to control five sensors. I thought I did it, but when I synthesized it, I saw that the code is synthesized as bunch of buffers and nothing else.

I think I do not understand what FSM can or can't do but I really couldn't find the problem.

 module RX_to_TX(
    input logic i_clk, i_reset,
    input logic[7:0] i_from_Rx , 
    input logic[7:0] i_Dev1 , i_distance_Dev1,
    input logic[7:0] i_Dev2 , i_distance_Dev2, 
    input logic[7:0] i_Dev3 , i_distance_Dev3,
    input logic[7:0] i_Dev4 , i_distance_Dev4,  
    input logic[7:0] i_Dev5 , i_distance_Dev5,
    output logic[7:0] o_Tx ,
    output logic o_Tx_DV
    );
    logic[7:0] next_Tx;
    logic[1:0] curState , next_State , DistanceState , StopState; 
    always_ff @(posedge i_clk )
        begin
            if ( i_reset == 1'b1)
                begin
                    o_Tx <= 0;
                    curState <= DistanceState;
                end
            else
                begin
                    o_Tx <= next_Tx;
                    curState <= next_State;
                end    

        end


     always_comb
        begin
             next_Tx = o_Tx;
             case(curState)
                DistanceState:
                    begin
                           if( i_Dev1 == i_from_Rx ) 
                                o_Tx = i_distance_Dev1;
                           if( i_Dev2 == i_from_Rx )
                                o_Tx = i_distance_Dev2;
                            if( i_Dev3 == i_from_Rx)
                                o_Tx = i_distance_Dev3;
                            if( i_Dev4 == i_from_Rx )
                                o_Tx = i_distance_Dev4;
                            if (i_Dev5 == i_from_Rx)
                                o_Tx = i_distance_Dev5;
                        next_State = StopState;
                        o_Tx_DV = 1'b1;
                    end
              StopState:
                begin
                    o_Tx = 8'b11111111;
                    o_Tx_DV = 1'b0;
                end
              endcase

        end
endmodule

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  • \$\begingroup\$ Did you define connections from your module's inputs and outputs to the physical pins of the FPGA? What warning messages did the synthesizer give you? \$\endgroup\$ Jul 26, 2019 at 19:53
  • \$\begingroup\$ Did it work correctly in simulation? \$\endgroup\$
    – user16324
    Jul 26, 2019 at 19:54
  • \$\begingroup\$ I did not connected to the fpga yet \$\endgroup\$ Jul 26, 2019 at 20:04
  • \$\begingroup\$ It works actually in simulation \$\endgroup\$ Jul 26, 2019 at 20:06

1 Answer 1

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Ok, I figured out my stupid mistake,

I changed the o_Tx to next_Tx in the nested case statement and it worked.

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