Understanding signed numbers in Verilog

Question

For my Verilog code, I am trying to define a 64 bit array, like this

input signed [63:0] var_name

This array is broken up such that it is 8 bytes, each with a width of 8 bits.

I am wondering how Verilog handles mathematics in this case. If I want to sum up all the different "bytes" of var_name, I try to do it like this:

module sum(var_name, sum);
input signed [63:0] var_name;
output reg signed [9:0] sum;

always @ * begin
sum = 0;
for(i = 0; i<8; i = i+1)
   begin
   sum = sum + var_name[8*(i+1)-1 -:8];
   end
end
endmodule

(note, this code may not be proper, it is just an illustration).

Does Verilog treat each 8-bit word as a signed integer? Or does Verilog only consider the entire word var_name as a signed word?

Thanks a lot for reading. I hope my question is clear enough! If not, please ask questions about it. :)

Answer 1

Only the entire declaration as a whole is considered signed. Selecting a bit or part-select (even if it selects the entire range) would be considered unsigned. That's because the base element data type of the array (reg) is unsigned.

SystemVerilog allows you to layer your types so that you could take a signed 8-bit type and pack it into a signed 64-bit declarations.

typedef logic signed [7:0] byte_t;
byte_t signed [7:0] var_name;