For my Verilog code, I am trying to define a 64 bit array, like this

input signed [63:0] var_name

This array is broken up such that it is 8 bytes, each with a width of 8 bits.

I am wondering how Verilog handles mathematics in this case. If I want to sum up all the different "bytes" of var_name, I try to do it like this:

module sum(var_name, sum);
input signed [63:0] var_name;
output reg signed [9:0] sum;

always @ * begin
sum = 0;
for(i = 0; i<8; i = i+1)
   sum = sum + var_name[8*(i+1)-1 -:8];

(note, this code may not be proper, it is just an illustration).

Does Verilog treat each 8-bit word as a signed integer? Or does Verilog only consider the entire word var_name as a signed word?

Thanks a lot for reading. I hope my question is clear enough! If not, please ask questions about it. :)

  • \$\begingroup\$ Why don't you write a testbench and try it? \$\endgroup\$ – Elliot Alderson Jul 27 '19 at 0:05
  • \$\begingroup\$ Hi Elliot, To be honest, it's been a while since I've used a testbench. I am using Xilinx System Generator, so it is block-based design. I got it to work though. I used an intermediate step in order to break up the input into a packed array register. This seems to work! \$\endgroup\$ – Lerbi Jul 27 '19 at 2:44

Only the entire declaration as a whole is considered signed. Selecting a bit or part-select (even if it selects the entire range) would be considered unsigned. That's because the base element data type of the array (reg) is unsigned.

SystemVerilog allows you to layer your types so that you could take a signed 8-bit type and pack it into a signed 64-bit declarations.

typedef logic signed [7:0] byte_t;
byte_t signed [7:0] var_name;
  • \$\begingroup\$ Thank you for the answer. If I have an intermediate step that uses a register to break it up into a packed array form, would the signed work then? I can't use SystemVerilog for my purposes. \$\endgroup\$ – Lerbi Jul 27 '19 at 2:29
  • \$\begingroup\$ Yes, you can always make intermediate variable assignments to get the effect of a cast. \$\endgroup\$ – dave_59 Jul 27 '19 at 3:03
  • \$\begingroup\$ Hi Dave, It seemed to fix my issue. It seems like an ugly workaround that wastes a bit of memory, but hopefully it doesn't waste too much. \$\endgroup\$ – Lerbi Jul 27 '19 at 3:04
  • \$\begingroup\$ That what you get for sticking with a 30 year old language. \$\endgroup\$ – dave_59 Jul 27 '19 at 5:45
  • \$\begingroup\$ All I gotta say is... Blame Xilinx. \$\endgroup\$ – Lerbi Jul 27 '19 at 6:04

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