I was looking through an old schematic and found two symbols that I didn't recognize:
Is this a PNP transistor? looking up the model number doesn't give much information.
Is this some kind of variable resistor or variable inductor?
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Sign up to join this communityI was looking through an old schematic and found two symbols that I didn't recognize:
Is this a PNP transistor? looking up the model number doesn't give much information.
Is this some kind of variable resistor or variable inductor?
- Is this a PNP transistor? looking up the model number doesn't give much
Building up on the comment of Harry Svensson and jonk, this is a mesa PNP transistor. The MESA technique, in the early days of the transistor, was a technique developed for improve the (then poor) HF response of the devices by removing those parts of the base region which, for their geometric structure, do not improve the \$\beta\$ current gain and rise too much the stored base charge \$Q_{bb}\$ and the base-collector capacitance \$C_{bc}\$, raising the switching time and lowering the cut-off frequency of the device, resulting in its general slowing down. The technique consist of etching of the semiconductor around the emitter and the base contacts: this creates a sort of plateau respect to the collector region on the wafer around these contacts, and the Spanish word for this is "mesa".
- Is this some kind of variable resistor or variable inductor?
This is precisely an analog delay line: it is a network which, within given frequency range and reasonable waveform distortion, produces at its output(s) a delayed version of its input signal, i.e. $$ v_o(t)=v_i(t-t_D) $$ where \$t_D\$ is the characteristic delay of the line. The model shown seems to be a multiple tap delay line i.e. a delay line offering \$n\$ outputs delayed respect to the input by increasing delay times, i.e. $$ \begin{split} v_{o1}(t)&=v_i(t-t_D)\\ v_{o2}(t)&=v_i(t-t_{D1})=v_i(t-(t_{D1}+t_{D2}))\\ v_{o3}(t)&=v_i(t-t_{D1})=v_i(t-(t_{D1}+t_{D2}))\\ \vdots\quad & \qquad\qquad\qquad\vdots\\ v_{oN}(t)&=v_i(t-t_{DN})=v_i\left(t-\sum_{i=1}^Nt_{Di}\right)\\ \vdots\quad & \qquad\qquad\qquad\vdots\\ \end{split} $$ In the case under examination, \$DE1\$ seems a 4-tap delay line where each tap adds a \$50\mathrm{ns}\$ delay respect to the preceding one.