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I was looking through an old schematic and found two symbols that I didn't recognize:

  1. enter image description here

Is this a PNP transistor? looking up the model number doesn't give much information.

  1. enter image description here

Is this some kind of variable resistor or variable inductor?

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    \$\begingroup\$ Welcome. Did you Google 2N2451 ? \$\endgroup\$ – Sparky256 Jul 27 at 5:49
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    \$\begingroup\$ Well one clearly says 2N2451, a germanium mesa PNP transistor. Not sure what mesa means. \$\endgroup\$ – Harry Svensson Jul 27 at 5:53
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    \$\begingroup\$ @HarrySvensson I'm older, so I kind of remember. The very first planar transistors were called mesa transistors; named after mesas found in the SW US. (A mesa is a broad hill with a very flat top and cliff-like sides.) The idea was a huge improvement over the older alloyed-junction BJT. \$\endgroup\$ – jonk Jul 27 at 6:29
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  1. Is this a PNP transistor? looking up the model number doesn't give much

Building up on the comment of Harry Svensson and jonk, this is a mesa PNP transistor. The MESA technique, in the early days of the transistor, was a technique developed for improve the (then poor) HF response of the devices by removing those parts of the base region which, for their geometric structure, do not improve the \$\beta\$ current gain and rise too much the stored base charge \$Q_{bb}\$ and the base-collector capacitance \$C_{bc}\$, raising the switching time and lowering the cut-off frequency of the device, resulting in its general slowing down. The technique consist of etching of the semiconductor around the emitter and the base contacts: this creates a sort of plateau respect to the collector region on the wafer around these contacts, and the Spanish word for this is "mesa".

  1. Is this some kind of variable resistor or variable inductor?

This is precisely an analog delay line: it is a network which, within given frequency range and reasonable waveform distortion, produces at its output(s) a delayed version of its input signal, i.e. $$ v_o(t)=v_i(t-t_D) $$ where \$t_D\$ is the characteristic delay of the line. The model shown seems to be a multiple tap delay line i.e. a delay line offering \$n\$ outputs delayed respect to the input by increasing delay times, i.e. $$ \begin{split} v_{o1}(t)&=v_i(t-t_D)\\ v_{o2}(t)&=v_i(t-t_{D1})=v_i(t-(t_{D1}+t_{D2}))\\ v_{o3}(t)&=v_i(t-t_{D1})=v_i(t-(t_{D1}+t_{D2}))\\ \vdots\quad & \qquad\qquad\qquad\vdots\\ v_{oN}(t)&=v_i(t-t_{DN})=v_i\left(t-\sum_{i=1}^Nt_{Di}\right)\\ \vdots\quad & \qquad\qquad\qquad\vdots\\ \end{split} $$ In the case under examination, \$DE1\$ seems a 4-tap delay line where each tap adds a \$50\mathrm{ns}\$ delay respect to the preceding one.

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  • \$\begingroup\$ Can a modern normal transistor be used instead of the mesa transistor? \$\endgroup\$ – person Jul 27 at 17:44
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    \$\begingroup\$ @person, from the point of view of strict performance yes, this is possible. However, the 2N2451 is a germanium transistor, therefore its bias network is designed to produce values of \$V_{BE}\$ which are incompatible with a modern silicon transistors. If you cannot obtain a 2N2451, search for an available equivalent germanium transistor or try to modify the biasing without changing other parameters. \$\endgroup\$ – Daniele Tampieri Jul 27 at 19:49
  • \$\begingroup\$ One more question. what is the top pin of the delay line for? \$\endgroup\$ – person Jul 27 at 22:25
  • \$\begingroup\$ @person, the terminal which is connected to the top in your schematics is the reference terminal of the input and outputs of the delay line. It is where all lumped capacitors inside the component are connected and, in most applications, it is connected to a voltage which is dynamically (i.e.for all AC signals) at the ground potential. However, as you perhaps you can see in your complete schematics, this is not mandatory. \$\endgroup\$ – Daniele Tampieri Jul 28 at 10:46

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