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I have the code for read write register here

module read_write(
input             clk     ,
input             rst_n   ,
input      [31:0] data_in , //data to be written
input             rw      , //rw=1->write to data_out; otherwise, read from data_out
output reg [31:0] data_out 
);



always @(posedge clk or negedge rst_n) begin
if(~rst_n)
  data_out<=0;
else begin
  if (rw)               //write to data_out
    data_out<=data_in;
end
end
endmodule

How can I read data from a register? I am a bit confused, if I don't write the data to the register, how can I read something from the register?

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  • \$\begingroup\$ Doesn't input [31:0] data_in, input data to register [31:0]? \$\endgroup\$ – Chu Jul 27 '19 at 10:43
  • \$\begingroup\$ @Chu, yes it does because when rw=1, data_out is written to. But how can I write the code to make data_out a read only register? \$\endgroup\$ – iuliana iuliana Jul 27 '19 at 10:47
  • 1
    \$\begingroup\$ All you have to do to make it read only, is omit the if (rw) data_out<=data_in; section. But in that case your code does not make sense. You always get 0 out (the reset value of the register). Thus you can replace the whole module with 32'h0; \$\endgroup\$ – Oldfart Jul 27 '19 at 12:37
  • \$\begingroup\$ @Oldfart, but how can I access some data from the register? To read its content at the given address... \$\endgroup\$ – iuliana iuliana Jul 27 '19 at 13:11
  • \$\begingroup\$ Initialise it to whatever constant value you want at reset. \$\endgroup\$ – Brian Drummond Jul 27 '19 at 14:38
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To read its content at the given address...

I suspect your code has been reduced a bit too much, it is not looking at all like a CPU interface. This might be a school assignment so I only provide an outline of the code. (Which, by the way, has not been syntax checked)

...
input [7:0] read_only;
...
reg [7:0] write_only;
reg [7:0] read_write;


always @(posedge clk or negedge reset_n)
begin
   if (!reset_n)
   begin // set reset value of registers
      ...
   end
   else // clocked
   begin
      if (cpu_write)
         case (cpu_address[2:0])
         3'b000 : write_only <= cpu_write_data;
         3'b001 : read_write <= cpu_write_data;
         endcase
      else
      if (cpu_read)
         case (cpu_address[2:0])
         3'b001 : cpu_read_data <= read_write;
         3'b010 : cpu_read_data <= read_only;
         endcase
   end // clocked
end // always 
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  • \$\begingroup\$ The read_only input is a status register from the system? Or what information does it hold? @Oldfart \$\endgroup\$ – iuliana iuliana Jul 30 '19 at 7:52
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"Read only" registers are generally used to get data into the CPU that's coming from somewhere else, such as status information from a peripheral interface. Such a register requires additional input port(s) to bring that data in from one or more other modules. That data may or may not need to be resynchronized to the CPU clock for correct operation.

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