# How can I transform the code for a read-write register to a read only register in Verilog?

I have the code for read write register here

module read_write(
input             clk     ,
input             rst_n   ,
input      [31:0] data_in , //data to be written
input             rw      , //rw=1->write to data_out; otherwise, read from data_out
output reg [31:0] data_out
);

always @(posedge clk or negedge rst_n) begin
if(~rst_n)
data_out<=0;
else begin
if (rw)               //write to data_out
data_out<=data_in;
end
end
endmodule


How can I read data from a register? I am a bit confused, if I don't write the data to the register, how can I read something from the register?

• Doesn't input [31:0] data_in, input data to register [31:0]? – Chu Jul 27 '19 at 10:43
• @Chu, yes it does because when rw=1, data_out is written to. But how can I write the code to make data_out a read only register? – iuliana iuliana Jul 27 '19 at 10:47
• All you have to do to make it read only, is omit the if (rw) data_out<=data_in; section. But in that case your code does not make sense. You always get 0 out (the reset value of the register). Thus you can replace the whole module with 32'h0; – Oldfart Jul 27 '19 at 12:37
• @Oldfart, but how can I access some data from the register? To read its content at the given address... – iuliana iuliana Jul 27 '19 at 13:11
• Initialise it to whatever constant value you want at reset. – Brian Drummond Jul 27 '19 at 14:38

I suspect your code has been reduced a bit too much, it is not looking at all like a CPU interface. This might be a school assignment so I only provide an outline of the code. (Which, by the way, has not been syntax checked)

...
...
reg [7:0] write_only;

always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin // set reset value of registers
...
end
else // clocked
begin
if (cpu_write)
3'b000 : write_only <= cpu_write_data;