consider this file : tb_sr_latch.v
`include "sr_latch.v" module tb_sr_latch; reg [4:0] t_in; wire out; sr_latch M1(t_in, t_in, t_in, t_in, t_in, out); initial begin $dumpfile("tb_sr_latch.vcd"); $dumpvars(0); t_in = 5'b00000; repeat(32) begin #1 t_in = t_in + 5'b00001; end end endmodule
and this file : sr_latch.v
module sr_latch(input set, reset, enable, preset, clear, output out); assign out = ((!clear && (preset || !(reset && enable))) && (!clear && (preset || (out || (enable && set))))); endmodule
I compiled tb_sr_latch.v with the following command:
iverilog tb_sr_latch.v -o a.out
and when I tried to run a.out with the following command:
it stuck [maybe] in a loop with this message:
VCD info: dumpfile tb_sr_latch.vcd opened for output.
Can anyone help me to solve my problem ? please tell me where Im wrong and why it happends, because I know it is possible to implement it with always block instead of using gates.