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I would like to get some understanding about the gate charge of a power MOSFET. I am referred to this MOSFET gate drive circuit application note: https://toshiba.semicon-storage.com/info/docget.jsp?did=59460 In page 5, subsection 1.2.3. Gate charging mechanism, they assert that Cgs and Cgd capacitances are charged in parallel but I didn't figure out why, normally the MOSFET is in off state and there is no short-circuit across its drain and source. Also, the figure 1.4 and 1.7 state that from time t0 to t2 only Qgs is involved!

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  • \$\begingroup\$ Qgs applies until Vds starts changing then Qdg takes over (becomes more dominant due to gm*(Vgs-Vt)) until the Vds transition is completed. \$\endgroup\$ Jul 28 '19 at 4:08
  • \$\begingroup\$ @SunnyskyguyEE75 Before reaching the miller plateau, Vds is pinned to VDD and Vgs rises linearly, so the voltage across Cgd decreases which makes Cgd discharge to VDD-Vgs(pl) afterwards Cgd takes over because there are no voltage changes seen across Cgs due to Miller effect. \$\endgroup\$
    – settimed
    Jul 28 '19 at 9:22
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When we think about transient behavior, we usually pin the VDD to a perfectly-fixed voltage. In reality, we have a huge capacitor from VDD to GND.

Thus when the circuit is charging the gate, the C_GS has charge flowing directly to GND.

And the C_GD has charge flowing into VDD, which has that huge capacitor to let the change in charge be flowing into GND.

For circuits that do not keep VDD in a well-controlled state, we tend to call those circuits oscillators, or expect warrantee-problems down the road because of un-reliable behaviors.

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  • \$\begingroup\$ You are talking about the huge capacitor from VDD to GND that causes a short when Cgd has charge flowing, but what about Cds? \$\endgroup\$
    – settimed
    Jul 28 '19 at 9:06
  • \$\begingroup\$ Cds will be two caps in series: C_drain_Bulk and C_bulk_source \$\endgroup\$ Jul 29 '19 at 3:26
  • \$\begingroup\$ In a discrete MOSFET, bulk and source are shorted together. \$\endgroup\$
    – jp314
    Oct 11 at 3:38
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When the device is "off". rising from 0V, Vgs charges both Cgs and Cgd as Vg is common to both, but it does not begin to conduct as defined by Vgs(th) =Vt until Vgs reaches that level of charge voltage.

"On" state resistance is an analog value, where RdsOn is then reduced towards the rated value as (Vgs-Vt)/Vt exceeds 2 to the rated for RdsOn @ Vgs usually in the 2~4 Vt range depending on the device threshold specs.

SO in digital terms, we think of On/Off state as a binary but that is only for specified binary Vgs levels with thresholds Vih,Vil (for CMOS) and tolerances like -10% for Vdd. But actually, it is an analog value that continuously varies.

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