I would like to get some understanding about the gate charge of a power MOSFET. I am referred to this MOSFET gate drive circuit application note: https://toshiba.semicon-storage.com/info/docget.jsp?did=59460 In page 5, subsection 1.2.3. Gate charging mechanism, they assert that Cgs and Cgd capacitances are charged in parallel but I didn't figure out why, normally the MOSFET is in off state and there is no short-circuit across its drain and source. Also, the figure 1.4 and 1.7 state that from time t0 to t2 only Qgs is involved!
When we think about transient behavior, we usually pin the VDD to a perfectly-fixed voltage. In reality, we have a huge capacitor from VDD to GND.
Thus when the circuit is charging the gate, the C_GS has charge flowing directly to GND.
And the C_GD has charge flowing into VDD, which has that huge capacitor to let the change in charge be flowing into GND.
For circuits that do not keep VDD in a well-controlled state, we tend to call those circuits oscillators, or expect warrantee-problems down the road because of un-reliable behaviors.
When the device is "off". rising from 0V, Vgs charges both Cgs and Cgd as Vg is common to both, but it does not begin to conduct as defined by Vgs(th) =Vt until Vgs reaches that level of charge voltage.
"On" state resistance is an analog value, where RdsOn is then reduced towards the rated value as (Vgs-Vt)/Vt exceeds 2 to the rated for RdsOn @ Vgs usually in the 2~4 Vt range depending on the device threshold specs.
SO in digital terms, we think of On/Off state as a binary but that is only for specified binary Vgs levels with thresholds Vih,Vil (for CMOS) and tolerances like -10% for Vdd. But actually, it is an analog value that continuously varies.