# Quartus Prime Lite: Generate a 25.18 MHz clock and Constrain to clock input in HDL

I am trying to use a generated clock in .sdc to drive my logic in my DE1-SoC Cyclone V chip. When I load the design onto the chip currently, nothing happens. My counter led does not even blink to show progression of the clock. I think it is an issue with constraints.

de1_soc.sdc

create_clock -period "25.18 MHz" -name clk_vga [get_ports VGA_CLK]


I get a warning

Warning (332174): Ignored filter at de1_soc.sdc(20): VGA_CLK could not be matched with a port

My top module looks like this

module vga_640_480(
input                 vga_clk,
input             rst_n,
input[2:0]        r_in,
input[3:0]        g_in,
input[2:0]        b_in,
output[7:0]       vga_r,
output[7:0]       vga_g,
output[7:0]       vga_b,
output                vga_blank_n,
output                vga_hs,
output                vga_vs,
output                vga_sync_n,
output                timer_test
);


At the same time in the .qsf I have the following

set_location_assignment PIN_A11 -to vga_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_clk


So I build the design and the .qsf is changed automatically with those two constraints above removed. So I commented out the line in the .sdc and readded the two constraints I had in the .qsf back in, but they are still removed when I rebuild. I also checked Pin Planner after the qsf is changed with those lines removed and it has constrained the vga_clk to A11 which appears to be correct. I really think my logic is correct (I should simulate it) and that the clock is messed up based on the constraints.