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When do we say that a nMOS or pMOS is "on" or "off"? Are there any voltages across terminals we should be looking for?

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For MOS, the voltage from gate to source, Vgs, controls if it is on or off. PMOS turns on when gate is lower than source by the threshold voltage, Vgs(th).

Let's say Vgs(th) = -2V for a particular P-channel MOSFET. Then whenever the voltage from gate to source is -2V or below, then the MOSFET is on.

For NMOS, Vgs(th) will be positive. Let's say it is +2V. Then whenever Vgs is > 2V, the N-channel MOSFET will be on.

Vgs(th) will vary and will be listed in the datasheet. Generally, in order to really turn the MOSFET on strongly, you will want to exceed Vgs(th) by a good amount to make sure you are solidly in the "on" region.

I would be remiss if I didn't mention the body diode at this point. There is an intrinsic diode built into MOSFET's. Even when it is off, PMOS allows current to flow (with one diode drop) from drain to source. And NMOS allows current to flow (with one diode drop) from source to drain.

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Just as logic has valid Logic in/out levels so do discrete FETs if you have a logical criteria. For 74HC CMOS with Vt=1.5 and Vdd=5V that is a certain ratio to ensure low Ron and good noise margins. The ratio ensures adequate Ron 5/1.5 but with lower Vt FETs a ratio of 2 to 2.5 may be adequate, but more is slightly better.

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  • \$\begingroup\$ I thought flow of drain current was a sure way of telling if a mosfet is "on" till i read about cmos inverters where if the input is low, the pmos device is "on" and the output of the cmos is high even though there is no current.. What is keeping the pmos "on"..? I am not sure what I am missing here \$\endgroup\$ – Nullbyte Jul 28 '19 at 4:13
  • \$\begingroup\$ Drain current depends on the load Resistance when Vdd/Ids=RdsOn + load and "on" depends on your personal acceptance criteria compared to the rated RdsOn at some Vgs >> Vt. If there is no load then you expect no output current on Ids. Maximum current occurs at no load @ Vdd/2 when there is cross-conduction in CMOS e.g. >~ 50 Ohms for xxx ns which is why all CMOS IC's need a decoupling cap. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jul 28 '19 at 4:36

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