RISC-V: building a datapath for conditional branch instructions

Question

I am simulating a multi-cycle 32bit RISC-V CPU in Logisim Evolution. So far so good. I have implemented almost every instruction from the basic RV32I ISA, but I'm having trouble understanding how the condition branch instructions work.

I want to implement:

1. Branch if equal (BEQ)
2. Branch if not equal (BNE)
3. Branch if less than (BLE)
4. Branch if greater than equal (BGE)
5. Branch if less than unsigned (BLTU)
6. Branch if greater than equal unsigned (BGEU)

I have read that the ALU uses 4 bits as input:

3bits: Funct3 or ADD or SUB with check for zero

1bit: 6th bit from funct7

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How (or where) is the branch generated? The ALU unit has a ZERO output, and it's anded with a control line to activate the branch, but the branch instructions have all different Funct3 codes, so that means it must be decoded somewhere.

Where is the calculation performed, for example for BGE/BGEU? We can calculate the BEQ just by subtracting the two numbers in ALU, but what for the others?

My simulation of the CPU for illustration:

Answer 1

The abstract behind the branch ISA's is that if the conditions are met, the program counter will JUMP to the given address. To implement a branch, the Branch generator must be correct and the PC source must be set to branch. To ensure the PC source is correct, a control unit decoder must be able to differentiate between the commands. That's where the opcode and the func3, func7 come into play. So the rundown pretty much goes like this.

1. Compiler breaks down the ISA into binary where the decoder uses that to determine the given instruction.
2. The control unit sets the muxes to the correct one.
3. The PC then moves to the correct address

The photo was taken from Cal Poly EE Department CPE 233 Assembly and Computer Design taught by Professor Joseph Callenes-Sloan.