I am simulating a multi-cycle 32bit RISC-V CPU in Logisim-Evolution and so far so good, i had implemented almost every instruction from the basic RV32I ISA. But im having trouble to understand how the condition branch instructions works.
I want to implement:
- Branch if equal (BEQ)
- Branch if not equal (BNE)
- Branch if less than (BLE)
- Branch if greater than equal (BGE)
- Branch if less then unsigned (BLTU)
- Branch if greater then equal unsigned (BGEU)
I have read that the
ALU uses 4 bits as input:
SUB with with check for zero
1bit: 6th bit from
So than how (or where) is the branch generated? The ALU unit has a
ZERO output, and its
anded with a control line to activate the branch. But the Branch instructions have all different
Funct3 codes, so that means it must be somewhere decoded.
And even than, where is the calculation performed, for example for
We can calculate the
BEQ just by subtracting the two numbers in ALU, but what for the others?
My simulation of the CPU for ilustartion
Thanks for any help.