I am simulating a multi-cycle 32bit RISC-V CPU in Logisim Evolution. So far so good. I have implemented almost every instruction from the basic RV32I ISA, but I'm having trouble understanding how the condition branch instructions work.
I want to implement:
- Branch if equal (BEQ)
- Branch if not equal (BNE)
- Branch if less than (BLE)
- Branch if greater than equal (BGE)
- Branch if less than unsigned (BLTU)
- Branch if greater than equal unsigned (BGEU)
I have read that the ALU
uses 4 bits as input:
3bits: Funct3
or ADD
or SUB
with check for zero
1bit: 6th bit from funct7
How (or where) is the branch generated? The ALU unit has a ZERO
output, and it's anded
with a control line to activate the branch, but the branch instructions have all different Funct3
codes, so that means it must be decoded somewhere.
Where is the calculation performed, for example for BGE
/BGEU
?
We can calculate the BEQ
just by subtracting the two numbers in ALU, but what for the others?
My simulation of the CPU for illustration: