I have had to layout 2 layer PCBs several times now for analog signals, and am just beginning to learn the process. I often face a similar question in one form or another with regard to laying out signal vs power tracks to avoid crossings, etc, and would like some advice.

I have provided the following dummy schematic to try help explain the question, as this is typical of the sort of thing I've done before. The circuit has the following parts: There is some input analog signal, which then passes through a series of components (in this case, inverting op amps with some gain) to manipulate the signal in some way, followed by an output. There are various resistors which are required in each stage, and also the signal is broken out at various points and sent to connectors. All stages require both the V+ and V- PSU connections.

enter image description here

My question is really about the high level approach to the layout in general, and in particular the power traces vs signal traces. If the components are on the top layer, and the bottom layer is to be flooded with a ground plane (not drawn), there are two obvious approaches I can see: you could either have the power traces brought to the chips on the bottom layer, and then up to the chips using vias (Approach A); or you could bring the power on the top layer and then take the signals to the bottom layer using vias when necessary to avoid crossings (Approach B):

enter image description here

Approach A) : This will in general allow all the signals and components to be kept compact and tight around each of the chips, and signals can be brought to connectors without requiring vias for them. The problem is that the power delivery is more elaborate, and the ground plane on the bottom layer is significantly cut up by the power tracks.

Approach B) : The power delivery here is tighter, without vias, and doesn't break up the bottom layer ground plane so much. The issue is that the signals have to pass through vias to avoid crossing the power.

So my question is what kinds of things should I be worrying/thinking about when faced with laying out power vs signal for such an analog board? How to think about which of these might be a better way to go for future projects? Is there actually a better approach to the layout that I haven't mentioned? Are there any pros or cons that trump all in these situations?

General advice and thoughts would be very welcome.

Extra info:

  • Let's assume that in reality there are also sufficient bypass capacitors for each chip, but they are not drawn in the interest of clarity.
  • My applications are generally sensitive to noise on the analog signals, but the bandwidths required are not high (on the order of hundreds of kHz).
  • \$\begingroup\$ I might avoid running analog signals along the path of power signals, like as you show in (A)R1->R2. Having them cross at 90° isn't too bad, but you should avoid running them along the power trace unless you have a ground plane separating them. \$\endgroup\$
    – Ron Beyer
    Jul 28, 2019 at 20:13
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    \$\begingroup\$ I notice you have no PSU decoupling caps at your ICs. As long as your crossings to the bottom layer are very short, as you've shown in B, that would be preferrable. A creates huge long cuts in the ground plane such that it's no longer functioning as a plane. Given the low incremental cost of 4 layers over 2, you might also want to consider a proper ground plane, and 3 layers for tracking. \$\endgroup\$
    – Neil_UK
    Jul 28, 2019 at 20:19
  • \$\begingroup\$ Is the position of the components fixed? Have you tried rotating the ICs by 90 degrees? At a quick glance, that could improve the layout. Don't forget to add the GND vias on the IC as well as some decoupling capacitors. \$\endgroup\$
    – Elmesito
    Jul 28, 2019 at 21:16
  • \$\begingroup\$ @Elmesito The components can indeed be rotated ofcourse, but I don't believe it allows avoiding the problem of having to cross tracks. Please note, this is not a real design, merely a "dummy" schematic to try to illustrate the general question I often find myself facing -namely Approach A versus B in general. As mentioned in the post, "let's assume that in reality there are also bypass capacitors for each chip". I really tried to distill the problem down to the simplest schematic I could, and so left out details such as the capacitors. \$\endgroup\$
    – teeeeee
    Jul 28, 2019 at 23:26
  • 1
    \$\begingroup\$ what precision of measurement do you need? What are the slewrates of possible interfering waveforms? \$\endgroup\$ Jul 29, 2019 at 3:33

5 Answers 5


In general I prefer to use a modified solution A, simply because it seems (in a first pass) easier (and cleaner) to route than B. The significant change (for my solution) is that both layers allow large copper masses similar to a plane to be used - why not include a copper pour on top?

In the following, I've increase the copper area for the power, and included (as commented earlier) bypass caps. Also important is that the power and ground vias were added immediately after placing the ICs. This sort of forces the designer to consider power routing sooner.

method-A, with larger copper pours

There is a copper GND pour on the bottom layer. And if I really feel like it, I will add a copper GND on the top (keeping with the notion that one cannot get enough GND).

To move the power pours closer to the ICs, move the resister stack to the right side of the ICs. Which leads to the next method B (also modified).

METHOD B (modified) =============================

  • push the resistor stack to the bottom layer.

  • do not have any trace run too long, thus there will be a generally "good" ground plane on the bottom.

  • pull the copper pours right up to the ICs.

(btw, all those vias in the original B were too much for me :)

methode B

Here is a view of the bottom layer (without the GND copper pour) enter image description here

Summary of changes to the original premises:

  1. Consider pouring more copper on the top layer to improve your power delivery.

  2. Consider using the bottom for components.

And of course:

  1. add bypass caps


C1. Method A is great for low power, typical opamp stuff.

C2. Method B is necessary for Motor Drives.


The thing you want to avoid if possible is to have your signal paths cross reference plane voids. You will also want to bypass both v+ and v- to ground, since you’re driving signals referenced to ground (SMA connector shield). Try adding bypassing and see how that works out. That said, approach (A) is more what I would choose.


I generally do the really critical nets first, then the local decoupling arrangements (Because they are actually reasonably critical), then the rest of the signal stuff, then fit the bulk power in at the end.

You are also doing yourself a bit of a disservice by considering the ground plane as a magic universal ground, it more or less works most of the time in digital things, and is not inherently horrible the rest of the time, but think about where the currents flow!

While your example is a little noddy to show this, I would actually treat the 'ground' to all those non inverting inputs as THE critical net which should have so far as I can manage no current flowing in it. In a more serious circuit this is hard to manage with just slapping things down to a ground plane. Net ties are your friends.

I would also be far more concerned with the design of the current loops, consider one of the middle opamps, current flows from one supply rail (Which one depends on which quadrant) thru the previous opamp, thru the resistors and then into the output of the next opamp in the chain before returning via the other supply rail. Significant decoupling is indicated at each opamp, and because the quadrant changes (and thus you get half wave current pulses in each rail) you should be careful about just how the bypass caps go to 'ground' to avoid injecting half wave rectified current pulses into your ground.


The answer is simple: it doesn't matter.

In both examples, there is the additional stray length ( = inductance, unless this is at such high frequencies that TL effects matter too) to signals, or power, which is to say the sum of both is about the same either way.

On a 2-layer board with well-stitched ground pour, prioritizing one layer for ground is a good idea, assuming you don't need other conditions like high density or a two-sided placement or anything. In that case, most traces route on the top, with vias to the bottom for short jumper traces as needed. In a complex design, this can end up taking a fair amount of routing area (escaping buses from MCUs for example; especially the kind where ports are scattered around the chip, ugh!), but it preserves a low ground impedance between locations, and given adequate spacing between traces, similarly keeps them in a nice consistent microstrip or coplanar waveguide with ground (CPWG) geometry, good up to quite high frequencies (thus including up to frequencies where TL effects take over).

...And that's without local bypass per chip!

For average audio op-amps, CD4000 family logic, even 74HC family to some extent -- lengths of several inches between loads and bypass caps will likely be fine.

Case in point: the original NES game console's controllers had a CD4021 shift register on them, no bypass cap, and >2m cable length! They passed, well -- granted, they passed whatever EMI rules were around in 1985, but I doubt the levels and methods were too much different from today. (Interesting question [if they were different], if anyone has a reference to add here.) CD4000 logic is slow as molasses at 5V, so it's no surprise it worked. 74HC is really where you'd want a limit of some inches, especially for higher current loads (bus drivers?), and so on as things get faster (74LVC, within a cm or two, etc.).

With local bypass, the PS routes are irrelevant. Well, sort of; they still contribute inductance between locations, so some damping may need to be applied, such as a ferrite bead from the common point, or an R+C (lossy or "bulk" cap) at the terminal ends / leaves of the network. With adequate losses in the network, its impedance is never much above the network's characteristic impedance \$Z_0 = \sqrt{\frac{L}{C}}\$, which we can design to be as low as we need. (Basically, being lazy about placing caps around, and the lengths between them, and between the chips, has the effect of raising \$Z_0\$. For general-purpose op-amps, a few ohms is more than low enough. Which is easily attained with a few 0.1µF's and electrolytics.)


The best practice for analog circuits is to reduce the loop area of the signal and its return path and keep the impedance as low as possible. WHen not possible then the impedances must be balanced to reduce the common mode noise becoming differential.

When there is no circuit noise or ambient noise, with low impedance there is no need for a ground plane. Noise voltage is simply noise current * circuit impedance. f (V(f)=I(f)*Z(F) where Z(L)=2piL for a short trace of 0.5nH/mm or a longer wire of 1nH/mm. (>40 l/d ratio)

enter image description here Although this mainly for RF or rise times< 20ns can you see the difference in signal+return loop area in the above?

You must learn to define specs for every design so you know what you can test to be sure it works. This includes stray spectrum and level of EMI in terms of uA/m or mV/m and slew rate or freq. of both. This includes SMPS, AC power , motors, switched inductors etc. near any cables. THen you need to specify spectrum and signal minimum level then finally minimum SNR required. THis includes DC offset which you can trim on 1st stage.

Putting the cable into a 10:1 scope probe can measure your stray voltage @ 10 MOhm load. Terminating it and then shunting an RF cap to earth gnd to reduce EMI levels. Finally using a telephony or LF/HF CM CHoke to further balance the signal for the frequency range of interest.

After all this is done, then look at the crosstalk in your logic and SMPS routing to high impedance signals, then even with this you may not need a ground plane. Even Yamaha Audio equipment designs can get away without this.

After you have done this then you can decide if you even need a ground plane, but you may always need an RF cap to AC ground to shunt low frequency line and SMPS common mode, CM noise.

Since you are using SMA connectors , I assume SNR is important and using the OP07 which has 75uV low input offset voltage with a few nA of bias current makes the input impedance very high. Yet grounding the other input makes the input very unbalanced. SO before you consider a ground plane make your signal balanced with a differential R ratio using 0.1% or better an INA arrangement of 3 Op Amps with > 100 dB CMRR. This is your first step to eliminating stray cable induced EMI. A pot can easily null DC offset, then with selectable single R's you can change gains with analog switches.

  • 2
    \$\begingroup\$ As I said in the post, the schematic was simply a "dummy" schematic to help with illustrating the question. The fact that I used SMA connectors, and the specific op amp part OP07, is completely irrelevant for the purposes of my question. The question was in regard to either taking the signals to the bottom layer using vias, versus taking the power rails to the bottom using vias. And to what are the pros and cons of my two described appraches A and B. \$\endgroup\$
    – teeeeee
    Jul 28, 2019 at 22:47
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    \$\begingroup\$ There is also no mention of any SMPS in my post, nor any digital logic (indeed, I explicitly talked exclusively about analog signals only). The example I gave was intended to be as abstract as possible. \$\endgroup\$
    – teeeeee
    Jul 28, 2019 at 23:00
  • \$\begingroup\$ Then that's just 1 less EMI source to be concerned about. Go look at your CD/DVD player and see if it has a ground plane and there are lots of motors nearby and a SMPS source. OA's are constant current low noise generators , that's another reason you don't need a ground plane but MAY NEED a balanced diferential source and load impedance, dpending on your specs \$\endgroup\$ Jul 29, 2019 at 0:32
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    \$\begingroup\$ "Go look at your CD/DVD player" is not a helpful response - I am trying to learn exactly what is fundamentally good or bad about the specific two layouts I have proposed, not some other scenario that you yourself have invented. If you have something to contribute with reference specifically to my original question, then that would be great. Otherwise, -1 for seemingly having not read the question properly. I don't know how much clearer I can be - if something is not clear, please let me know and I will edit the question accordingly. \$\endgroup\$
    – teeeeee
    Jul 29, 2019 at 9:54
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    \$\begingroup\$ I was rather hoping that more experienced people than myself may have gut reactions when seeing these layouts - of which I find myself having to do quite often - and say "X is generally a bad idea", or "Y is a good thing to do". These are things that I don't usually find in textbooks, and there is no substitute for experience. I am aware of the example you gave of minimising the loop area by allowing the return current to flow directly beneath the signal, if at all possible. In fact, there is a beautiful and spectacular demonstration of this here: sigcon.com/Pubs/news/8_08.htm \$\endgroup\$
    – teeeeee
    Aug 1, 2019 at 20:34

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