I have had to layout 2 layer PCBs several times now for analog signals, and am just beginning to learn the process. I often face a similar question in one form or another with regard to laying out signal vs power tracks to avoid crossings, etc, and would like some advice.
I have provided the following dummy schematic to try help explain the question. There is some input analog signal, which then passes through a series of components (in this case, inverting op amps with some gain) to manipulate the signal in some way, followed by an output. There are various resistors which are required in each stage, and also the signal is broken out at various points and sent to connectors. All stages require both the V+ and V- PSU connections.
My question is really about the high level approach to the layout in general, and in particular the power traces vs signal traces. If the components are on the top layer, and the bottom layer is to be flooded with a ground plane (not drawn), there are two obvious approaches I can see: you could either have the power traces brought to the chips on the bottom layer, and then up to the chips using vias (Approach A); or you could bring the power on the top layer and then take the signals to the bottom layer when necessary to avoid crossings (Approach B):
Approach A) : This will in general allow all the signals and components to be kept compact and tight around each of the chips, and signals can be brought to connectors without requiring vias for them. The problem is that the power delivery is more elaborate, and the ground plane on the bottom layer is significantly cut up by the power tracks.
Approach B) : The power delivery here is tighter, without vias, and doesn't break up the bottom layer ground plane so much. The issue is that the signals have to pass through vias to avoid crossing the power.
So my question is what kinds of things should I be worrying/thinking about when faced with laying out power vs signal for such an analog board? How to think about which of these might be a better way to go for future projects? Is there actually a better approach to the layout that I haven't mentioned? Are there any pros or cons that trump all in these situations?
General advice and thoughts would be very welcome.
- Let's assume that in reality there are also sufficient bypass capacitors for each chip, but they are not drawn in the interest of clarity.
- My applications are generally sensitive to noise on the analog signals, but the bandwidths required are not high (on the order of hundreds of kHz).