There are different ways to wait on a signal change in VHDL. In my testbench I need to wait on a signal but if it does not change in say 100us, then I must continue the test. How to do this?


1 Answer 1


You can just combine a wait for with a wait until statement. For your example:

wait until your_bestie_signal`event for 100us;

This will return when an event is registered on the signal or 100 microseconds of simulation time have passed.

  • \$\begingroup\$ Wow its that simple? I wonder why none of my books or resources mention this. \$\endgroup\$ Jul 29, 2019 at 13:03
  • 1
    \$\begingroup\$ @Quantum0xE7 Dunno, it's vaguely explained in my Doulos VHDL Golden Reference Guide and you can find some tutorials if you search for "vhdl wait until for", but honestly, I just remember reading the syntax in a SystemC test-bench tutorial where they mentioned that sc_core::wait(a, b) is equivalent to wait until a for b. \$\endgroup\$
    – DonFusili
    Jul 29, 2019 at 16:11
  • \$\begingroup\$ It's not combining them, one is a condition clause the other is a timeout clause. See IEEE Std 1076-2008 10.2 Wait statement. A condition is an expression providing a Boolean value. An explicit timeout clause provides a time expression, which for an implicit timeout clause is TIME'HIGH. Note the standard also requires a separator between an numeric literal and an identifier as in the answer's time expression (15.2). \$\endgroup\$
    – user8352
    Jul 29, 2019 at 16:58
  • \$\begingroup\$ A time expression isn't a lexical element and there is a -2008 lexical element (Bit string) where the lack of a separator can be ambiguous despite a couple of commercial implementations treating time expressions as lexical elements. \$\endgroup\$
    – user8352
    Jul 29, 2019 at 17:10
  • \$\begingroup\$ @user8352 Feel free to edit or provide a more correct answer, it's been years since I wrote a VHDL test, so I'm sure you're right. \$\endgroup\$
    – DonFusili
    Jul 30, 2019 at 7:57

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