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I do not understand the following memory map regarding the NVIC registers in Programming Manual for STM32f103 page 129. It says that the offset address for NVIC_IPR0 is 0x300 and that of NVIC_IPR20 is 0x320. I do not understand how is this possible?! I think that the offset for NVIC_IPR20 should be 0x350. Indeed, assuming the registers follow one after another one obtains something like this:

NVIC_IPR0 -> 0x300

NVIC_IPR1 -> 0x304

NVIC_IPR2 -> 0x308

etc.

NVIC_IPR20 -> 0x350

What am I doing wrong?

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You're correct -- that looks like a typo. The offset for that register should be 0x350.

The CMSIS header file (core_cm3.h) avoids the issue entirely by defining NVIC->IP as an array of bytes, not of 32-bit words:

__IO uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */

This documentation error was probably the result of confusion between the byte-wise structure used by ARM and the 32-bit structure used by ST.

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  • \$\begingroup\$ Sir, by the way, why the IP has 240 values? There, in the programming manual I see that there are just 21 registers each having 4 bytes, therefore it seems that IP[84] should have been enough ... right? \$\endgroup\$ – C Marius Jul 30 at 19:37
  • \$\begingroup\$ For the STM32F103, yes, that'd be sufficient. But the CMSIS header was written by ARM to support any Cortex-M3 microcontroller, not just this one; as such, it's been put together to support up to 240 interrupts (which I believe is the most the architecture could possibly support). \$\endgroup\$ – duskwuff Jul 30 at 19:40
  • \$\begingroup\$ ok, thank you very much! \$\endgroup\$ – C Marius Jul 30 at 19:42

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