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I have a microsecond timer (generates interruption every microsecond) for which I implemented a "HAL_TIM_PeriodElapsedCallback" function. What occurs if the execution of the callback function takes longer than a microsecond?

PS: I'm using an STM32F030F4Px mcu with st-link v2 debugger.

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The HAL timer interrupt handler does not do anything special, it checks all possible pending interrupts, clears them and runs the callback. So it is not re-entrant. If your callback takes longer to run than the timer period, the interrupt has to wait until callback and handler are finished to run again, so during this time the interrups are missed and it will only run as many interrupts per second it can.

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  • \$\begingroup\$ I see. So it doesn't save all the interrupts on the stack causing it to overflow? \$\endgroup\$ – DTl Jul 31 at 8:23
  • \$\begingroup\$ @DTl No, interrupts pending are signalled by a bit in a register, there is no count of how many times a particular interrupt has happened. \$\endgroup\$ – Colin Jul 31 at 8:46
  • \$\begingroup\$ No. Not by default anyway. But if you really want to have one million interrupt callbacks per second and they always take more than 1 microsecond to execute, have you considered it might be a bit wrong approach to begin with? \$\endgroup\$ – Justme Jul 31 at 8:47
  • \$\begingroup\$ Yes. I'm also pretty sure my callback doesn't take more than a us to execute. Was just curious what would happen. \$\endgroup\$ – DTl Jul 31 at 9:38
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Firstly, if execution time for interrupt handler is longer than the interrupt period itself (1 uS in your case), then its bad design. Make sure that interrupt handler does not do anything thats not essential to be done in the handler itself. Other tasks should be relegated to your state machine, and most the timer ISR should do is set a state or a flag.

Secondly, if that still happens to be the constraint you want to deal with, then although the timer is configured to interrupt at a rate of every 1 microsecond, due to the latency in handling the previous such interrupt, you are going to miss out on the latest interrupt. There is no de facto mechanism that can/should stack up the interrupts from the same peripheral and service them later one after another, neither you can/should keep track of such events.

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  • \$\begingroup\$ Thank you for the response. What my goal is to measure the time of execution of some instructions. What i figured i would do is start a timer and in the callback function I increment a counter to know how many us have passed. I figured that using interrupts would overwhelm the execution of the rest of the code. So I am trying currently to use a timer without interrupts and get the counter start value and counter stop value. \$\endgroup\$ – DTl Jul 31 at 9:44
  • \$\begingroup\$ @DTI: I would have not used timers for that. The easiest way of doing that could be setting a GPIO pin on start of the event and clearing it the end of the event. Get an oscilloscope, measure the pulse duration. \$\endgroup\$ – WedaPashi Jul 31 at 13:41
  • \$\begingroup\$ That's exactly what I did. I wanted to double check. But oscilloscope values seem more precise and consistent. \$\endgroup\$ – DTl Jul 31 at 13:57
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Other answered what happened with interrupt routine, but what is also important is what happen with regular code. When MCU get interrupt signal it stop executing regular code and jump to interrupt routine (+some overhead) and when it finished with interrupt routine it resume regular code. As interrupt routine and main code cant run concurrently too many interrupts mean that your interrupts use all of your CPU cycles and stop your regular code from executing.

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  • \$\begingroup\$ Yes.I know about the push and pull operations on contexts. I am currrently trying to use a timer without interrupts to satisfy what i need. \$\endgroup\$ – DTl Jul 31 at 9:40
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You can measure short time periods without interrupts by taking a snapshot of a free running timer counter register before and after the events you want to time, then subtract to get the difference.

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  • \$\begingroup\$ And if it overflows/underflows during that process? Just for ONE owerflow a mod(end-start,ARR+1) maybe enough but for more than 1 overflows I think it might be a problem. \$\endgroup\$ – muyustan Aug 4 at 6:14
  • \$\begingroup\$ How can i make sure that +1 in the counter register is a +1 us ? \$\endgroup\$ – DTl Aug 5 at 10:48

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