0
\$\begingroup\$

I don't know if this question is a good question to get answers or not but I am trying to honestly explain my situation.

I am studying 8085 microprocessor, so I am stumbled upon address decoding circuits. As I was looking over past year questions, I saw many questions like the one I asked above are being asked in exams.

Then, I started to read books and pdfs all over the internet and knew the uses of address decoding, and other basic concepts such as memory mapped i/0...etc

Now, my confusions are

1) How to find the ending address for these 2 devices?
2) How to design a proper circuit for it?

This may be too broad, but I believe that many students are facing similar problems. Though this is not the place for homework solving but due to lack of good materials around the web, I am here and I am optimistic to get a complete solution.

\$\endgroup\$
1
\$\begingroup\$

First have a look here: http://searle.hostei.com/grant/index.html . You will see how a decoder circuit looks like. Whatch also for additional I/O devices, each circuit has an enable or chip select active on a range of address:

enter image description here

1) How to find the ending address for these 2 devices? 2)and how to design a proper circuit for it?

Arbitrary selection in the available address space for RAM, while ROM shall be at the reset vector.

2)and how to design a proper circuit for it?

By doing truth tables, you can separate address ranges so that you have a minimal gate count for decoder circuit. It would be nice, in your project to have RAM addresses contiguous.

https://iemcse.files.wordpress.com/2017/07/cs502snscm4.pdf

enter image description here enter image description here

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.