To follow up on the excellent answer of Enric Blanco, I provide the adage of my semiconductor layout mentors: "The layout is the real schematic."
To improve the matching of Rs and Cs and transistors, do the following:
1) have identical layouts, including what is surrounding the component; in other words, do not expect matching between two resistors embedded in a random bucket of other implants; the lateral diffusion of those other implants will affect the carrier density of the dopants in the two (we need these to match) resistor volumes.
2) do not expect matching across the wafer or across the die or even from adjacent doped or etched regions; if you expect matching, then interdigitate the pieces of the resistors (or capacitors, or transistors).
3) for successful matching, you need to tolerate the edge-etching and edge-doping variations; this requires significant widths in resistors and in capacitors and in transistor active regions; do not expect minimum-width structures to match; thus in a 0.1 micron process, do not use that minimum width (or length) for precision components
4) I've seen people's circuits provide excellent matching of very small components in over-sampling ADCs, because during the over-sampling behavior the capacitors were pseudo-randomly switched in and out
5) in capacitors, the fringing fields must also be matched; that requires "dummy" capacitors be used to surround your capacitor-array
6a) you must match the temperature environment; learn to create thermal shorts on silicon (heavy metal) to minimize the temperature gradients
6b) learn to map the heat flows; be responsible; put the high-heat components ON ANOTHER CHIP; don't punt and hope --- have test chips to learn of what is possible
6c) learn to create thermal opens on chip, at least at the surface
6d) expect to have to match the METAL environment; this requires AREA to play with, around the must-match region; as you might expect, precision will cost you
6e) if you do not know the lateral thermal-resistance of your various metal layers (standard 35 micron PCB copper is 70 degree Centigrade per watt per square, any size square; 1 micron copper will be 35*70 = 2,400 degrees per watt per square), then you are not a serious matching-is-my-goal designer
7) circuits can make decisions very quickly; do you know how the thermal transients affect the matching? 1 micron cubes of silicon have 11.4 nanosecond thermal time constants.
"The layout is the real schematic" because the physical-layout lets the system designer and the circuit designer and the layout designer manage the variances.