It would be theoretically possible for an FPGA to write a configuration image to an external memory, and load the configuration image from the memory to reconfigure itself. This would be "non-dynamic" reconfiguration.

Do FPGAs have the ability to rewire their logic fabric dynamically? Indeed, while flip-flops can have their value modified, I have not heard of dynamic reconfiguration of the look-up tables and internal wirings that make up the logic fabric.

Can FPGA internal logic (other than memories) be dynamically modified? If not, why not?

  • \$\begingroup\$ "dynamic reconfiguration" is indeed the phrase you are looking for :) \$\endgroup\$ – Martin Thompson Oct 22 '12 at 10:32
  • \$\begingroup\$ Are you looking for FPGAs that can reconfigure themselfs (like some microcontrollers can) or that they can be reconfigured (runtime) from an external component? \$\endgroup\$ – Trygve Laugstøl Oct 24 '12 at 14:03

Yes, I know that at least Xilinx has parts that support dynamic reconfiguration, and the other major vendors probably do, too.

It's a major undertaking to do it, though, so you really need to make sure you need it. You need to partition the chip physically into two or more areas, at least one of which is non-reconfigurable, and physically "pin down" all of the internal interfaces among the areas so that the synthesis tools can make all the right connections.

  • 1
    \$\begingroup\$ Search the Xilinx web site for "reconfigurability"! \$\endgroup\$ – Leon Heller Oct 20 '12 at 18:00

There are two general approaches one can use. Many types of FPGA hold their configuration in latches which are fetched from an external device (typically an EEPROM) on startup; the external device is not needed by the FPGA after it has been read. Changes to the EEPROM during device operation will not take effect until the FPGA is instructed to reload its contents. Thus, it's possible for a device which would be completely inoperable without an FPGA to reprogram that FPGA during operation; if something goes wrong during the EEPROM write, however, the device may be inoperable unless or until can be rewritten by an external device (a state sometimes referred to as being 'bricked').

An alternative approach, which is often useful with CPLDs whose EEPROM cells "directly" control their functionality (as opposed to being copied to latches) is to have a system which can operate with limited functionality even when the programmable device is in a useless state. If such limited functionality is sufficient to reprogram the CPLD, the device may be be immune to 'bricking'. For example, a wireless device might use a CPLD to control its wireless functionality and other features. The normal method of reprogramming the CPLD might be to receive an image into RAM via the wireless link, and then use that image to reprogram the CPLD. If programming files, the wireless link may be unusable until the CPLD gets reprogrammed. To allow the system to recover, however, the processor could contain a "default" image for the CPLD which would include enough functionality to operate the wireless link.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.