There are two general approaches one can use. Many types of FPGA hold their configuration in latches which are fetched from an external device (typically an EEPROM) on startup; the external device is not needed by the FPGA after it has been read. Changes to the EEPROM during device operation will not take effect until the FPGA is instructed to reload its contents. Thus, it's possible for a device which would be completely inoperable without an FPGA to reprogram that FPGA during operation; if something goes wrong during the EEPROM write, however, the device may be inoperable unless or until can be rewritten by an external device (a state sometimes referred to as being 'bricked').
An alternative approach, which is often useful with CPLDs whose EEPROM cells "directly" control their functionality (as opposed to being copied to latches) is to have a system which can operate with limited functionality even when the programmable device is in a useless state. If such limited functionality is sufficient to reprogram the CPLD, the device may be be immune to 'bricking'. For example, a wireless device might use a CPLD to control its wireless functionality and other features. The normal method of reprogramming the CPLD might be to receive an image into RAM via the wireless link, and then use that image to reprogram the CPLD. If programming files, the wireless link may be unusable until the CPLD gets reprogrammed. To allow the system to recover, however, the processor could contain a "default" image for the CPLD which would include enough functionality to operate the wireless link.