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I have a question about this paper: https://ieeexplore.ieee.org/document/1210630

I have always thought that the maximum current ripple of a buck converter occurs with a duty cycle of 0.5. The paper on page 1373 shows in figure 3(a) that the maximum current ripple occurs at a duty cycle of about 0.6. Does this mean that the current ripple does not always reach its maximum value at a duty cycle of 0.5 or did the author make a mistake or did I misunderstand the diagram?

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  • \$\begingroup\$ 1. The article you linked to is behind a paywall. 2. The chart doesn't seem to say anything about buck converters. All the traces are labeled with the names of different kinds of converters. \$\endgroup\$ – The Photon Aug 1 at 19:58
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    \$\begingroup\$ The trace half-bridge is the one. Between a voltage ration 0 - 1 it operates as a buck converter. \$\endgroup\$ – Noah Aug 1 at 20:09
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I don't think these accurate without all the other variables like DCR, RdsOn ESR on both Caps, battery ESR, and load impedance.

I simulated a 75 to 250kW Half-bridge and the ripple current was negligible compared to the DC current at high load. I used an almost ideal SPDT switch so I did not need diodes.

I tried open loop with Duty cycle control and crude negative feedback with an RCRC divider and Offset V in the ramp comparator operating at 20kHz to get 150~300V in and 300V out.

With this arrangement the half-bridge showed little or no sensitivity to duty cycle for Inductor ripple as the load current was high. Meaning operating in CCM mode.

Perhaps these are NO-LOAD and I did not understand the question. enter image description here

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  • \$\begingroup\$ The author has neglected the losses, as in the paper he compared the topologies. I am surprised that in your simulation the current ripple did not change with the duty cycle. \$\endgroup\$ – Noah Aug 13 at 16:02
  • \$\begingroup\$ I suspect that was due to negative feedback with variable DC input voltage, FWIW @Noah \$\endgroup\$ – Sunnyskyguy EE75 Aug 13 at 16:48
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The author has assumed a constant input current and input voltage (in this case the bus current and voltage). With this assumption, the current ripple curves and the equations in the paper are correct.

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