I am trying to simulate a LNA circuit from the book "Design of CMOS RF Integrated Circuits and Systems"

However, the LNA circuit still does not give POSITIVE GAIN.

Any help ?

lna circuit

  • \$\begingroup\$ Are you using the right type of caps :)? \$\endgroup\$
    – Sorenp
    Aug 2, 2019 at 6:03
  • \$\begingroup\$ Try doing an AC sweep and showing the result. \$\endgroup\$
    – Andy aka
    Aug 2, 2019 at 7:06
  • 1
    \$\begingroup\$ Where’s your load? And add a source impedance too. \$\endgroup\$ Aug 2, 2019 at 8:09
  • \$\begingroup\$ I don' think 1nH inductors EVERYWHERE is a real design. 1nH at 1HGz is only j6.3 ohms, which is NOT a good bias-inserter. \$\endgroup\$ Aug 2, 2019 at 15:15
  • \$\begingroup\$ @analogsystemsrf, First I calculate j15 ohms instead of j6.3. Second, It looks like maybe they're going for (near) resanance with the 3 and 5 pF capacitors. Which I don't know if it's clever or stupid. \$\endgroup\$
    – The Photon
    Aug 2, 2019 at 16:27

1 Answer 1


Vgate of M1 is at VDD, that, together with the voltage drop across M2 forces it into linear mode. You want to use M1 in saturation mode. I would use something like this to have better control over the DC biasing current through M1:


simulate this circuit – Schematic created using CircuitLab

Note how M1bias and M1 form a current mirror, this allows me to directly set the DC biasing current through M1 by setting the value of I1.

R1 is a high impedance for the RF signal so M1bias doesn't see the RF signal. All RF signal goes to M1, which is what we need.

I biased the gate of the cascode transistor Mcasc with a separate DC voltage source. That way I can easily play with the value (in your circuit it is always VDD which is less flexible).

Note how I use C1 and C2 (both 1 nF) to block the DC signals. This works two ways, the LNA circuit isn't disturbed by any DC voltages at the input source or the output. The inputs and outputs will have a DC voltage of 0 V.

Small point: Ca does nothing in your circuit, it is directly in parallel with the the 1.8 V DC power supply which is an ideal voltage source so Ca will have 1.8 V DC across it as that is forced by the DC source. If you want to model the effect of a supply with an internal resistance then add resistor in series with the 1.8 V DC source and the Ca will help as it will decouple the VDD line to GND.

  • \$\begingroup\$ Why M2 needs to be in linear mode ? \$\endgroup\$
    – kevin
    Aug 2, 2019 at 9:10
  • \$\begingroup\$ Are you sure M2 is in linear mode? Think about what the DC voltages should be, then simulate them (do a DC operating point simulation) and see if they are what you think they should be. The first step in the design of any amplifier is to get the DC biasing correct. Only when that is done does it make sense to look at the AC transfer and Gain. Think about what happens to the Gain when a transistor isn't biased properly. \$\endgroup\$ Aug 2, 2019 at 9:23
  • \$\begingroup\$ What do you think about the AC response of updated LNA circuit ? \$\endgroup\$
    – kevin
    Aug 5, 2019 at 5:24
  • \$\begingroup\$ What I do not understand is the strange AC response in the previous post just above with a sharp magnitude dip and abrupt 180 degrees phase shift at 2.9GHz The transient response looks normal though. \$\endgroup\$
    – kevin
    Aug 5, 2019 at 9:22
  • \$\begingroup\$ If you want to design LNAs then such things should be "obvious" to you. What kind of circuit would show such a response? Can you draw the small signal equivalent circuit of your LNA? What components influence the behavior over frequency? A transient analysis shows the behavior at the frequency which you apply to the circuit, if you apply a frequency that is not exactly at this 2.9 GHz dip how would you the dip? \$\endgroup\$ Aug 5, 2019 at 9:29

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