My project involves the ESP32 and Ethernet. To get basic functinallity I intend to use the LAN8720 PHY because it is supported by ESP-IDF out of the box. But I also want to try out the KSZ8863RLL 3-port Ethernet switch instead of the PHY, which would enable the device to be spliced into existing TP cabling.
I'm asking how to best connect the phy and switch to the RJ45 magjacks (HR911105A), in a way that allows either of the ICs to be used. (and also not spew EMI all over the place)
For example I haven't found anything on joining differential pairs using 0Ω resistors.
My restrictions are:
- 2 layer 1.6mm thick PCB
- 5mil minimum trace size and spacing
- 0.3mm minimum via size
- Components only on one side
My attempt uses differential coplanar waveguides with ground (not poured). With 10mil track width and 5mil spacing between tracks and ground.
Arbitrary transmission line calculator (atlc) results:
create_bmp_for_microstrip_coupler 10 5 5 60 1.4 1 4.8 outc.bmp && atlc -S out.bmp out.bmp 3 Er_odd= 2.538 Er_even= 2.660 Zodd= 51.222 Zeven= 106.943 Zo= 74.012 Zdiff= 102.444 Zcomm= 53.472 Ohms VERSION=4.6.1
The connection jumpers between KSZ8863RLL and what would be LAN8720's RJ45 jack are placed as close to the PHY as possible to avoid stubs, but to do so they have to be placed on the bottom side - breaking my restriction. The connection to the jack pins is also not pretty, but that's more down to the jacks themselves.
The obvious improvement to the routing is to remove the PHY altogether, but that would mean the KSZ8863RLL would have to work with the ESP32. (I would appreciate any info on that, so far I know that port 3 has to be switched to MAC mode using their modified MIIM/SMI) Right now it seems more like an option for version 2.
Next would be using smaller resistors on the differential lines and changing the geometry under them to match the pad width.
Swapping TX and RX (to avoid crossings) and relying on Auto MDI-X to fix it could also be an option.
125MHz differential pairs should definitely be possible on 2 layer PCBs, as evidenced by the GS105 Gigabit Ethernet switch (also using underrated magnetics), taken apart in this answer. Of note is that it doesn't have any components on the differential pairs. Also it is interesting is the lack of a ground plane under the chip itself.
Last thing is the rule to maintain 1 inch between the PHY and magnetics (or magjacks). It supposedly reduces EMI, and i remember someone talking about PHYs producing common mode noise. Since to my knowledge the signals are purely differential (odd mode), why not do the same as NETGEAR and remove the ground around the chips and keep all that common mode noise inside?
For example doing that on my design: odd mode impedance goes up to 56Ω, while even mode increases 3 times to 302Ω.
out.bmp 3 Er_odd= 2.580 Er_even= 2.155 Zodd= 56.785 Zeven= 302.176 Zo= 130.993 Zdiff= 113.570 Zcomm= 151.088 Ohms VERSION=4.6.1