High/ Low level output voltage in gate driver datasheet

Gate driver datasheet mentions about VOLL and VOH with test conditions Iol=100mA

I am testing this using this setup by calculating value (ron of pmos is 7.05 ohms) of load to be placed, Is this the right test setup to check this parameter/ what is the functional meaning of this?

I am also testing peak pullup and pull down current which i got approximately proper result and mentioned in datasheet(dc and transient analysis) LM5102 figure 6.

• for excitement, insert 5 nanoHenry inductors GND and VDD pins of the gate driver. This begins to indicate the real-world behavior and waveforms. Also insert 10,000 picoFarad capacitor (the well-channel capacitance of the FETs) between GND and VDD. Enjoy the ringing. And reduce the pulsewidth to 100 nanosecond, with period of 200 nanosecond. – analogsystemsrf Aug 4 at 23:43

No, you should replace R1 with a constant current source of 100mA. If the direction of current is toward ground then use a value of 100mA for the $$\V_{OH}\$$ test and -100mA for the $$\V_{OL}\$$ test.
The basic meaning of the $$\V_{OL}\$$ specification is: How low (in voltage) can the driver pull the output pin while sinking 100mA? The maximum value given is the worst-case, or highest possible voltage that can appear when the driver is trying to pull the output pin low. Likewise, the $$\V_{OH}\$$ specification tells you how high can the driver pull the output pin while sourcing 100mA. However, this datasheet doesn't specify the actual voltage for $$\V_{OH}\$$ but rather the difference between the actual output voltage and its ideal value (either $$\V_{DD}\$$ or $$\V_{HB}\$$).