I'm studying this kind of CMOS switch:

I have some doubts about some sentences of my book.

1)

"For many analog applications, a switch is used merely to transfer a charge from one node to another and to set a voltage on a high impedance point."

What does it mean "high impedance point"? In our switch I just see a capacitor at the output node, but the impedance of a capacitor is not necessarily high

2)

"With the switch in Fig. 2.17 in the on state, after a transient, we have Vout=Vin hence the drain to source voltage of M1 goes to zero. The MOS enters the linear region and its on-resistance is approximated by

[...] We assume an exponential response of the circuit (we neglect any operation in the saturation region)"

The concept that, after a transient, the drain to source voltage goes (ideally) to zero is clear: indeed, assuming the capacitor initially discharged, the current which flows through the capacitor charges the capacitor and the output voltage increases, thus reducing the drain to source voltage. Moreover, if Vds is very small, the author replaces M1 with a resistor, thus obtaining an RC circuit. What is then the meaning of the sentence "we neglect any operation in the saturation region"?

3)

"The value of the source voltage is equal to the input signal. When the input approaches the gate control, the overdrive diminishes and, at a given level, vanishes. At this point, the on-resistance goes to infinity and the switch no longer operates properly."

Why does the author assume that the source is the left terminal of the mosfet (indeed he neglects Rin, thus the input voltage is equal to the source voltage)? Assuming M1 to be an NMOS, theoretically I don't know which terminal the source is: in an NMOS the drain is at a higher potential than the source, but who knows here which terminal is at higher potential? Indeed, if Vin suddenly increases, the output will be a little lower than Vin, thus the left terminal of M1 should be the drain.

4)

It seems that the author of my book assumes a constant input signal. Can the input be, in general, a variable signal (e.g. a sinusoidal signal)?

Thank you

What does it mean "high impedance point"? In our switch I just see a capacitor at the output node, but the impedance of a capacitor is not necessarily high

The impedance of the capacitor indeed depends on the frequency of operation. The author is implying that we are working at sufficiently low frequencies (i.e. much below $$\\frac{1}{2\pi R_{in}C}\$$) that we can consider the capacitor to be high impedance element.

What is then the meaning of the sentence "we neglect any operation in the saturation region"?

The switch is not always in the linear/triode region. In fact, if $$\V_{in}-V_{o} > V_{GS} -V_T\$$, then MOSFET is in saturation region. Here, the capacitor charging is linear in time: $$I=C\frac{dv_o}{dt}$$ $$v_o=\frac{It}{C}$$ This obviously is assuming that the current is constant, which in-turn assumes input voltage is constant, since $$\I=\frac{k}{2}(V_{G}-V_{in}-V_T)^2\$$. This charges the output node and the MOSFET enters the triode region when $$\V_o\$$ is sufficiently close to $$\V_{in}\$$.
After this, the MOSFET is a linear resistor and the whole circuit is equivalent to R-C circuit where $$\R=R_{in}+R_{on} \approx R_{in}\$$, since the switch resistance should be small. The capacitor charging is exponential in this region. The author is assuming that the charging is mostly exponential and that the linear charging time is negligible in its comparison.

Why does the author assume that the source is the left terminal of the mosfet (indeed he neglects Rin, thus the input voltage is equal to the source voltage)?

As explained before, the author is assuming the linear operation of the transistor where $$\V_{ds} \approx 0\$$, so the source and drain are at the same potential, it does not matter which one you use as the source. The input is easier to consider as the source as the voltage is known there, allowing us to calculate the switch resistance.

It seems that the author of my book assumes a constant input signal. Can the input be, in general, a variable signal (e.g. a sinusoidal signal)?

You can assume the input to be sinusoidal as well. For proper operation of the switch, it is required that the amplitude of the sinusoid is much lower than the gate voltage of the MOSFET, allowing it to be sufficiently "on", in other words, allowing its resistance ($$\R_{on}\$$) to be low (in comparison to $$\R_{in}\$$).
If this is not the case, you will see distortion at the output of the sample and hold circuit. This of-course can be solved by using the boot-strapping technique.

1) when the capacitor is charged, there is no current flow, thus appears as high impedance

2) the assumption is that the capacitor is charging to be equal to the input voltage, thus there is no voltage across the FET, and with zero voltage across the FET the operation is certainly in TRIODE

3) when the capacitor is fully charged, the left and right ends of the FET channel are at the same potential;

4) yes, the input signal can be changing, but the capacitor voltage will be lagging behind because of the charging timeconstant; the resistance will be NOT be 1/gm if the FET is not in triode regions. As the input voltage moves up and down, the gate-channel voltage will change, and the 1/gm will change, thus the timeconstant will change.