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I'm studying this kind of CMOS switch:

enter image description here

With the switch in Fig. 2.17 in the on state, after a transient, we have Vout=Vin hence the drain to source voltage of M1 goes to zero. The MOS enters the linear region and its on-resistance is approximated by

enter image description here

Assuming that the gate voltage is driven by a clock signal, we have the problem of the charge injection: when the clock goes down, the transistor M1 turns off and the charge of the channel splits approximately into two. Half of the charge goes toward left (i.e. the low impedance path), instead half of the charge is deposited on the top plate of the capacitor, thus causing a voltage drop at the output (which, as a consequence, becomes smaller when the switch M1 is off). When M1 turns on again (i.e. high level of the clock), the output voltage returns to be equal to the input voltage.

The book on which I'm studying proposes some solutions to alleviate the charge injection; among these, the following circuit is reported:

enter image description here

The problem is that I don't understand how this circuit works: the author of my book just explains how this circuit behaves with the charge injection problem (when M1 turns off, half of the channel charge goes to the inverting terminal, causing an offset at the input of the op-amp; but at the same time also M2 turns off, thus half of the charge of the channel of M2 goes to the non-inverting terminal and, thanks to the high CMRR, no problem occurs at the output), but he does not explain how this circuit works as a switch. I assume that the working principle of this circuit must be more or less the same of the "original" switch of Figure 2.17, but then why do we have an integrator circuit? Does M1, when it is on, work in the linear region (and thus is equivalent to a small resistor) as in the "original" circuit of Figure 2.17? In the "original" circuit of Figure 2.17, when the transistor is on, vout=vin; in the circuit of Figure 2.24, when M1 is on, we have an integrator circuit and thus a linear output voltage (and thus vout cannot be equal to vin).

Thank you

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    \$\begingroup\$ This circuit is not an integrator but an amplifier with gain \$\frac{C_2}{C_1}\$. So, it samples and amplifies the input voltage and is called "Sample and Hold Amplifier". \$\endgroup\$
    – sarthak
    Commented Aug 6, 2019 at 13:30

1 Answer 1

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I think the complete circuit for the image you show should look like this.

schematic

simulate this circuit – Schematic created using CircuitLab

The circuit works in two phases, \$\phi\$ and \$\overline{\phi}\$. The figure indicates the phase when the switches are on.
In the \$\overline{\phi}\$ Phase
The input voltage is sampled on the capacitor \$C_2\$. Note that \$V_{out}\$ will be ground due to the feedback. So, you cannot use an operational amplifier for its implementation but a \$G_m\$ stage.
In the \$\phi\$ Phase
Capacitor \$C_2\$ is shorted and all its charge appears on the \$C_1\$ capacitor, giving a gain of \$\frac{C_2}{C_1}\$.
This type of circuit is useful since it combines sampling and amplification of input voltage in one circuit which relaxes the resolution requirement of the following stage in ADC.
I think you already understand how it cancels the charge injection. So, hopefully it answers your question.

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