If I need to perform the same function on a number of different signals in a VHDL design will placing them in a vector affect synthesis optimization in any way?
As as example, let's say I'm trying to simulate a real-world circuit that's built up from TTL chips. A 7402 Quad 2-Input NOR chip, for example, can have the logic for each gate specified explicitly:
entity dm7402 is port( a0, a1, a2, a3, b0, b1, b2, b3: in std_logic := '0'; y0, y1, y2, y3: out std_logic ); end dm7402; architecture behavior OF dm7402 IS begin y0 <= a0 nor b0; y1 <= a1 nor b1; y2 <= a2 nor b2; y3 <= a3 nor b3; end architecture;
Alternatively I can use a vector:
entity dm7402 is port( a, b : in std_logic_vector(3 downto 0) := "0000"; y : out std_logic_vector(3 downto 0) ); end dm7402; architecture behavior OF dm7402 IS begin y <= a nor b; end architecture;
Intuitively I would guess that the first case could result in a faster design by giving the synthesizer the freedom to move gates around so as to optimize routing, whereas the second might result in using less resources. Is that a fair assumption to make?
(BTW I do realize that in a real-world situation I wouldn't actually be explicitly designing with TTL logic like this, but just humor me).