For a university module we have been tasked with a 'research project' whereby we need to implement an FPGA non-uniform variate generator. I've identified one possible choice for the specific distribution I was assigned - the Rayleigh distribution. I'm now trying to deduce if this design from literature will be possible for me to implement as a 16 bit version. I will be using a Terasic P0082 Cyclone IV De0-Nano which is a much simpler board than the one the authors used.

I have very limited exposure to FPGA and VHDL and so it is difficult for me to judge the complexity of implementing this design. On the surface it looks tame but the specifics of implementing the State Memory, Addressing Unit and Coefficient Memory in VHDL are unknown to me.

My question to more experienced FPGA designers is what they think of the complexity of this design. Is this something that would be easily implementable on the FPGA mentioned above for an undergraduate student or will this be a significant challenge?

The implementation from literature is based on the Box-Muller method and was implemented on a Xilinx Virtex-55VFX200TFF1738 FPGA. The design comes from A. Alimohammad, S. F. Fard, and B. F. Cockburn and their paper titled "Hardware Implementation of Rayleigh and Ricean Variate Generators". In the paper they give the design as:


Variate Generator

  • 2
    \$\begingroup\$ 1/ Looking at the diagrams, neither would suffice to implement the algorithm. You would need a lot more details of the boxes (Coefficient memory, ALU, State memory.) 2/ "Would this be do-able for an undergraduate student?" That would be an opinion. I have seen very clever and very stupid undergraduate students. \$\endgroup\$ – Oldfart Aug 7 '19 at 11:33
  • \$\begingroup\$ @Oldfart Thank you, that addresses my main concern - that not enough detail is provided to be able to successfully implement. I should have probably phrased the question as such. However the authors do give reference to the procedures they used to calculate coefficients, I will have to do some more research into that. \$\endgroup\$ – Blargian Aug 8 '19 at 6:43
  • \$\begingroup\$ First, write the algorithm part in a normal programming language. Make sure it works there. Then move it to an FPGA implementation. No sense in debugging the algorithm itself in HDL, just the implementation. \$\endgroup\$ – alex.forencich Aug 8 '19 at 8:43

my main concern - that not enough detail is provided to be able to successfully implement. I should have probably phrased the question as such.

Most important is if the papers describe the algorithm fully and in sufficient details.

I have done a lot of algorithm to Verilog conversion.
My approach is first to convert the algorithm to C, test it en then convert C to Verilog. Of course for the first phase I have the advantage, that with a lot of HDL experience, I know pretty well what C constructs can easily convert to HDL. (It also help that Verilog and C look a lot the same.)

The C model also help with debugging, it allows you to quickly verify where your HDL code produced different/erroneous results.

  • \$\begingroup\$ Thank you. This gives me a good place to begin. \$\endgroup\$ – Blargian Aug 9 '19 at 9:48

The abstract of the paper gives the resource utilization, which is very minimal; additional details are given in the body of the paper. There clearly would be no problem fitting this into any FPGA that has block RAM and hardware multipliers.

The Cyclone IV may or may not be able to achieve the same raw speed as the Vertex-5 — how important is that to you?

  • \$\begingroup\$ Not being able to achieve the same speeds is not important. The emphasis of the project is to pose some research question based on a proven design so this will contribute to the results. I'm more worried that not enough information is provided in the paper for me to be able to successfully implement. \$\endgroup\$ – Blargian Aug 8 '19 at 6:41

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