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schematic

simulate this circuit – Schematic created using CircuitLab

I have a circuit as seen in the schematic above. It has 4 different output stages. Each one has an "Enable" pin. The user is able to freely use the mechanical switch to enable any of the output stages. When an output stage is not enabled, its all output pins become Hi-Z. All output stages have a common output connector, and their output pins are shorted together at the output connector side. Therefore, only one of output stages must be enabled at the same time. According to the datasheets of the ICs I used in the output stage circuits, the output pins tolerated short time period of short circuit. So, there is no need to handle the transition between different user choices.

Now, my problem is, I don't trust the mechanical switch. If it fails and enables more than one of the outputs at the same time and it stays like that for a long time, there will be big damage on the circuit.

Can you suggest me a logic circuit which uses least amount of ICs to guarantee that always only one of the enable signals will be logic-1?

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  • \$\begingroup\$ Instead of doing that, how about a failsafe where if the switch fails and more than 1 output goes high, it turns that 'Allow All' signal low, which will shut down all the AND gates? Then you can investigate the problem. Or are you looking to completely get away from the switch? \$\endgroup\$ – MCG Aug 7 at 10:10
  • \$\begingroup\$ The AND symbols you use do not have the "Hi-Z" behavior you describe. I mean, your circuit doesn't match your functional description. What behavior do you want when more than one output is enabled? The use of a microController comes to mind unless there's a specific IC which can do this already (I don't know if one exists). \$\endgroup\$ – Bimpelrekkie Aug 7 at 10:13
  • \$\begingroup\$ @MCG Interesting. I am considering it. Can you suggest a simple logic circuit for detecting if more than one of four signals are logic-high? \$\endgroup\$ – hkBattousai Aug 7 at 10:22
  • \$\begingroup\$ @Bimpelrekkie The AND gates are not the output stages. I edited the schematic to make things clear. The desired failure behavior is not important. I just want to make it that the circuit is not damaged. \$\endgroup\$ – hkBattousai Aug 7 at 10:22
  • \$\begingroup\$ @hkBattousai if you decide on a failsafe, its easy enough to draw up a truth table or K-map and derive a logic circuit from them. Although the answer by Transistor may well use less gates. You could also use a binary encoder/decoder, or even a MUX instead of a mechanical switch. Or are you intending to keep the switch in the design? \$\endgroup\$ – MCG Aug 7 at 10:39
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I'd feed the 4 switch signals into a 74HC148 priority encoder, which outputs a binary number indicating which switch is active. This would go to a 74HC238 decoder which converts this back to 4 signals.

This ensures only one output at a time is enabled, and you can use the chip's ENABLE signals for additional control if required.

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    \$\begingroup\$ Solution with only two chips! This was what I was looking for. Thank you. I also thought about using multiplexer/demultiplexer pair, but gave up on it. Because, I had totally forgotten about existence of such a thing named priority encoder. \$\endgroup\$ – hkBattousai Aug 7 at 11:56
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schematic

simulate this circuit – Schematic created using CircuitLab

Figure 1. Solution based on understanding of question.

It seems as though much of the problem could be eliminated by using a reliable switch.

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