When doing rtl design, mux is always used to select the input of a block/module, for example:
input [135:0] dataA, dataB;
assign FIFO_DATAIN=(sl)?dataA:dataB;
myfifo xxx(.(FIFO_DATAIN)
.... );
Since the input data is 136 bits wide, this may lead to timing violations and requires a lot of resources after synthesis. Would it be better to use the "case" or "if else"? If not, is there a better way? Thanks in advance
It really doesn't matter how you write the code, it will be synthesized to the same thing. A 136 bit 2:1 mux is really not that bad. It's really the number of inputs that really dictates the complexity and causes timing issues, not so much the width, though that does place a large fanout on the select signal. If that was a 2 bit 136:1 mux, then maybe you could run in to issues. I have a design with lots of 256 bit wide muxes and it works just fine at 250 MHz. Also, the tools could the muxes that get inferred there and combine them with downstream logic.
One thing that you might want to take a look at, though, is where that mux ends up in the logic and where the select line is coming from. If the select signal is the result of a large, complex operation and the mux is directly feeding a lot of complex logic, then you could run in to timing issues unless you move the mux further down that logic and/or add a register on the select line.
I don't think it matters. Synthesis will smash this down to 136 2:1 muxes regardless of how you describe them in HDL. That's not that much in the larger scheme of things if you're building something with that large of a datapath (128 data, 8 enables, right?)
Insert register slices if it needs help to close timing.
Just as Hacktastical said, the synthesis will implement this with 136 small muxes. What I'd like to add is the issue may be about the 'sl' signal which will connect with 136 muxes. If the muxes are far from each other physically, it may be difficult for 'sl' signal to meet the timing requirements of each mux connected. If there is timing violation, you can try to insert FFs to separate 'sl' to several control signals. Each control signal connects with fewer muxes.
One way to avoid the timing problems of a big wide mux is to pipeline the selection if that meets your latency requirements.
