I am using a 555 timer for a (16bit) frequency sensor/counter.
It works by counting the number of pulses read in the 125ms sample time set by a 555 timer; resets & repeats...
I am using the timer in astable operation.
TH (time pulse high) is the sampling ON signal.
This time is set and trimmed (+/- 5% adjustment range) with a high quality POT.
TL (time pulse low) falling edge initiates a data-latch read --> then a counter reset operation
Right now I have it on a bread board. I am making a PCB for the final design and I want to iron out the following problem for the PCB design.
Here is the problem:
The measured frequency is not super stable (+/- ~3Hz @ 25kHz) and it takes a while to settle.
I think it is because the sample time is getting affected by the noise on the Vdd rail. I have decoupling caps on all the IC's but it is on a bread board so this can be expected. For the PCB layout I want to insure the 555 timer is on a solid 5v and the DCDC converter output is steady.
Here are some ideas I have on how to do this.
- Use a rail-rail opamp and 4v7 reference to regulate the Timer Vdd @ 4v7
- Use ferrite beads to further decouple the Timer and all the other ICs from each other.
- Use a seperate DCDC converter for the timer.
- Use a linear regulator IC for the Timer Vdd.
Which of these would be the best practice for insuring a constant timer Vdd value?