I consider writing a small program for the ARM Cortex-A9 in the Xilinx Zynq-7000 FPGA, so the program will be small enough to fit into the 32 KB L1 instruction cache. The data will also be less than 32 KB, thus can fit into the L1 data cache.

I expect it to be a very linear program, thus without penalty for branch misprediction etc. Also I expect there will be no data dependency within the length of the pipeline, or that bypass will be able to provide the data.

Is the L1 instruction cache fast enough so I can get an execution speed of at least at least 1 Instruction Per Cycle (IPC)?

Is the L1 data cache fast enough so data load and store access will not have any affect on the execution speed of at least 1 instruction per cycle (IPC)?

  • \$\begingroup\$ Isn't the IPC rate of most application processors already above 1 IPC? \$\endgroup\$ – MadHatter Aug 12 '19 at 14:32
  • \$\begingroup\$ @MadHatter: Good point; I have changed the question to say at least 1 IPC, since the A9 is multi scalar, though for my use it will be fine just to know that at least 1 IPC is always possible. \$\endgroup\$ – EquipDev Aug 12 '19 at 14:37
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    \$\begingroup\$ @EquipDev I can't speak to the ARM family. But in the case of the Pentium II, where I do have knowledge, just reaching the L1 cache required 3 clocks. Keep in mind that with the instruction decoder up to three instructions per clock could be decoded, the registration station supported two integer operations, two FP operations and up to two bus operations simultaniously in one clock, and the retire unit could retire up to 3 instructions per clock, as well. So the L1 cache, the fastest of the two caches on the P II, was still 3 clocks per. (The L2 was 6.) \$\endgroup\$ – jonk Aug 12 '19 at 15:47
  • \$\begingroup\$ Have you asked Xilinx this question? What do they say? \$\endgroup\$ – Elliot Alderson Aug 12 '19 at 18:22
  • \$\begingroup\$ @ElliotAlderson: Sure, I could post it in the Xilinx forum... I have not done that... SO came to my mind first ;-) \$\endgroup\$ – EquipDev Aug 12 '19 at 20:41

The L1 latency is a question for Xilinx since it depends on the implementation, or you can measure it as referenced in this question.

For a general overview of the L1 memory system, you can check the TRM. There is a 64 bit instruction datapath, which means a limit of 2 instructions fetched per cycle. Decode is also limited to 2 per cycle. Dispatch width depends on the instruction type.

For stores, there is a 4 entry store buffer, and being OoO, the pipeline shouldn't need to stall for a store even if the address isn't ready. Loads are the most critical accesses for latency, and you ideally want to be doing 64 bit loads.

Continuous load/store IPC of 1 is certainly feasible if you are not using any registers for data processing. IPC of nearly 2 might require that you pay a lot of attention to the dependancies and ordering if your data throughput is high (rather than mostly ALU operations).


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