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While trying to implement an IoT solution using a quad-band mobile network module, supporting GSM,UMTS,LTE (2/3/4G), I advised to add all the following capacitor values to the modules power bus.

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I have read several EE-SE answers on the subject and now understand that they are used for decoupling and evening out both LF and HF noise variations on the power bus.

Some relevant posts include:

To summarize briefly:

  • Large Capacitors handles low frequency noise and output load changes.
  • Small capacitors handle noise and fast transients.
  • Parallel capacitors results in a lower Equivalent Series Resistance (ESR) than a single capacitor of larger value.
  • LF capacitors (with higher ESR) have good performance in a wider range of frequency.
  • Using multiple capacitors would not only reduce reduce the heat generated (by ESR), but would also help spread the heat.
  • A decoupling capacitor is not only chosen by its Capacitance, but also by its ESR (Equivalent Series Resistance) and its ESL (Equivalent Series Inductance).

Q: (a) How are these values determined?

Q: (b) Why does small capacitors handle transient noise better than larger ones?

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    \$\begingroup\$ Have you watched the EEVBlog tutorial on bypass caps? Go here: youtube.com/watch?v=BcJ6UdDx1vg&t=685s \$\endgroup\$ – Bimpelrekkie Aug 13 at 14:38
  • \$\begingroup\$ Caps store 1/2CV^2 Joules of energy. Decoupling caps store energy to be supplied as charge during RF transmission events and local transients. Say you need 10W of power for 1us during a transmission that's 10 uJ of energy. Lets say your voltage is 5V then you would need 800 nF of capacitance (using the energy storage formula), but charge delivery is also limited by ESR and ESL so you have to use variously sized capacitors to supply energy during different transient states of your transmitter. \$\endgroup\$ – Captainj2001 Aug 13 at 15:18
  • \$\begingroup\$ I was hoping to see something more about how the selected cap values relate to the frequency of the noise. Since \$V_c=V_s e^{-t/\tau}\$ where \$\tau = R_{ESR} * C\$ and so on... And using the internal model for \$C = C^* + L + R^*\$. \$\endgroup\$ – not2qubit Aug 14 at 16:08
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    \$\begingroup\$ once I looked over the shoulder of a person designing a PCB for 900MHz and 1600MHz cellphone LocalOscillator rail bypassing. The person was guided to pick specific capacitors for which the self-resonance was known on a specific PCB foot-print (so the inductance was predictable). \$\endgroup\$ – analogsystemsrf Aug 15 at 6:48
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    \$\begingroup\$ @analogsystemsrf Not only that, some manufacturers, like Murata, provide you with the S-parameter files, which you can then directly import into ANSYS or the like. \$\endgroup\$ – user110971 Aug 15 at 7:48
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You are somewhat misguided about the purpose of decoupling. It is not mainly the noise that is problematic. ICs, especially digital ones due to the harmonics of the current pulses that they draw from the power supply, need a low impedance power source. This is because the MOSFETs inside the ICs draw virtually all of their current when they are switching and they are all switching at the same time. The problem is that if you remove the capacitors, the impedance between the IC and the power supply will be too large. Hence a voltage drop will develop and the voltage at the power pins will move outside the allowable range. Another problem is that the current will not be able to rise fast enough and the IC will be starved.

So how do you determine what capacitors to use? For low frequency applications you can just use some rules of thumb, but for high frequencies you need to be more careful.

Firstly, an impedance profile is created for the IC. This is determined by looking at the allowable voltage range in the specification. You can assume that a digital IC, for example, draws its current in the form of pulses that are around 10% of the period. You can then take the Fourier transform of the pulse (you get a sinc) and calculate the required power supply impedance.

Secondly, S-parameter files are either downloaded from the capacitor manufacturer or are created by testing various capacitors. The impedance profiles of capacitors look like this:

capacitor impedance

source

Finally, FEM simulation is done in something like ANSYS SIWave for power integrity. Diffferent configurations are attempted by first placing virtual capacitors on the imported PCB from your CAD package and then editing the PCB in your CAD package and re-importing it into SIWave. This is done until you satisfy the target impedance profile and suppress all the resonances (the planes can form resonant cavities) in the power planes.

This is how it’s supposed to be done anyway. Not everyone does it this way, but if you follow this procedure, you can make sure that your board works and passes compliance testing on the first try.

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  • \$\begingroup\$ I like this answer the beast as it has a more intuitive clear explanation. \$\endgroup\$ – not2qubit Aug 15 at 13:25
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Selecting decoupling capacitors isn't an "exact science", the exact values do not matter. Many engineers just use capacitors which they already use elsewhere in their design (to keep the BOM shorter).

Small value capacitors need less compromises to fit an amount of capacitance in a small space so in a small value capacitor we could for example use thicker conductive plates so that the series resistance becomes smaller. Simply put: small value capacitors can be made "more ideal" with less compromises due to size restraints.

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There is the brute force method or exact science method

  • The brute force usually relies on experience of which caps have a maximally low ESR over a 1 or 2 decades of freq or high SRF, so values are spread this far apart over the spectrum of interest using an impedance (\$Z\$) map vs \$f\$.

  • for a more exact design, you need to know how to test a prototype for ingress, egress to know how much ripple spectrum suppression is needed

    • the sensitivity of conducted voltage noise spectrum to performance error (phase noise, jitter etc) in [\$dBmV\$ vs \$f\$]
    • the load regulated error noise voltage spectrum in same method or using dV/dt method

Otherwise you can analyze load impedance and sensitivity to error, then design/choose caps with source ESR, \$\tau= R_{ESR}*C\$ of each to be much lower in [dB ohms] than source R or load R changes.

This means a solution with high impedance load or a short low resistance load with a short spike current can be solved by dV/dt+ I*ESR and possibly choosing a large source impedance like xx Ohms to supply power with a smaller low ESR cap.

I would approach this with Bode plots for each part or use S-parms from Mfg. or use real RLC simulation for each Cap, supply and load then perform startup and transient tests using a circuit simulator (for example in falstad), where there are filter design Bode plots and electronics DSO time domain simulation.

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