How to drive a clock signal to 20 digital microphone. The clock is generated from FPGA and about 3MHz frequency. First mic's line 2cm and last one's 15cm away from FPGA clock out pin. Also all mics should be sync.

  1. FPGA drive strength could adjustable, but can it still drive 20 mics at this distance?
  2. I found some clock driver, fanout buffer and similar ICs. Can someone who has experience give me an IC recommendation? Also if i need, how to locate it in PCB?
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    \$\begingroup\$ By itself driving 3MHz for 15cm is not an issue, but many important details is missing. How much does the mic clock input loads the signal, and can the FPGA drive the total load with sharp enough rise and fall times? Post the mic and fpga part types please. \$\endgroup\$ – Justme Aug 14 at 17:00
  • \$\begingroup\$ A 7 series FPGA and mp45dt02 from ST. \$\endgroup\$ – Berker Işık Aug 14 at 17:07
  • \$\begingroup\$ 7 series of what FPGA manufacturer? Altera? Lattice? Xilinx? Microsemi? \$\endgroup\$ – Marcus Müller Aug 14 at 17:08
  • \$\begingroup\$ Voltage level of clock signal is 3.3V LVTTL. \$\endgroup\$ – Berker Işık Aug 14 at 17:09
  • \$\begingroup\$ Oh, Xilinx 7 series. \$\endgroup\$ – Berker Işık Aug 14 at 17:09

At 3 MHz rise times should be easy to maintain with the distances involved. In my experience most digital lines need a driver if the fanout is more than 5 or 6, and definitely more than 10.

To determine fanout, one needs to know the source current of the driver pin and the sink currents of the receiving pins. The capacitance of the sinks also needs to be considered. One also needs to know what the voltage levels are of source and sink.

  • \$\begingroup\$ And, 15cm is half a foot; that's half a nanosecond on a PC board. If your clock is 3MHz, I don't see an extra half nanosecond as being an issue. \$\endgroup\$ – TimWescott Aug 14 at 17:14
  • \$\begingroup\$ Yes, estimated delay is 700-800 picosecond. \$\endgroup\$ – Berker Işık Aug 14 at 17:18

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