I am going to be ordering this board from JLCPCB which has some 0.2 mm hole diameter thermal vias on a QFN pad, and it says on their capabilities page that the smallest via hole size is 0.3 mm, BUT smallest drill hole size is 0.2 mm (2 layer board rules). It's a 2 layer board, they're actually not vias, they are pads which connect from front copper layer to bottom ground layer, I'm using the footprint from standard KiCad library "QFN-16-1EP_3x3mm_P0.5mm_EP1.75x1.75mm_ThermalVias". Do you think the board house will accept this? Or should I just make the hole diameter 0.3 mm? But if I do that will they be too large and will too much solder leak down through during reflow? I'll be soldering by hand with a heat gun, not an oven. Thanks for any advice.

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Here's the email response from JLCPCB:

"Thank you for your email. So sorry to tell you that we don't make via in pad. We make plated through via.(See pictures) Also,i find an instruction about our company. Instructions for ordering Hope this will help you. Thank you.

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So to me that sounds like they will make the vias in the pads but won't fill them with non-conductive material, which is all I wanted to do anyway. Although she didn't say specifically that they could do the bare via in the pad, which leaves me still a bit uncertain. I don't see why they couldn't though, just like a via anywhere else.

Also, I found this TI application note that recommends thermal pad vias be 0.3 mm or smaller, so should be good with the size.

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    \$\begingroup\$ NOTE: This is a "Via in pad" and not everywhere do these -- JLCPCB do not list "via in pad" as a capability \$\endgroup\$ – JonRB Aug 14 '19 at 23:45
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    \$\begingroup\$ Incorrect - they might be vias in a pad but they are not "via in pad", don't use those words or you will pay for a higher class service than you need. Just expand the holes to the minimum so they get manufactured with plating. Think of it more like a through hole connector footprint with multiple ground pins. \$\endgroup\$ – Chris Stratton Aug 15 '19 at 14:44
  • \$\begingroup\$ Thanks Chris that makes sense, and thanks Jon for raising the issue. \$\endgroup\$ – wdbwbd1 Aug 15 '19 at 14:48
  • \$\begingroup\$ @ChrisStratton its not incorrect, it is bringing to attention the concern. It is not advisable to have via's in pad as solder will wick down the holes and cause problem (tilting, inability to lay flat). This pushes the issue to assembly. "Via in pad" is the method used to correctly do this and can have plugged via's but mostly just cap them. Not all places will cap in-house as it relies on grinding the via's back level to ensure the pad is flush. \$\endgroup\$ – JonRB Aug 15 '19 at 17:28
  • \$\begingroup\$ Practically speaking, you are wrong. These are routinely done with open holes, making them something quite distinct from "via in pad". Remember it goes the other way too: a paste cutout the full size of the die pad area can easily supply so much solder that the part floats on it rather than seats correctly. \$\endgroup\$ – Chris Stratton Aug 15 '19 at 21:54

they are pads which connect from front copper layer to bottom ground layer

You've just described a via.

Do you think the board house will accept this?

If they're on the ball they won't accept it. They specify a hole size because below that their process won't reliably plate the holes. Do you want your thermal vias to be non-thermal holes?

Or should I just make the hole diameter 0.3 mm?

You should make the hole diameter 0.3mm, and accept difficulties in soldering. I'm guessing at this, but if you pre-fill the vias (by soldering them full) you may save yourself some grief in reflow. Or if you're using paste, just make sure they're packed full.

Finally (thanks, @ThePhoton): consider just using a different fab house. 0.2 mm vias is a pretty common capability these days. (Or ask the current fab house if they can do 0.2 mm vias with a cost premium)

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  • \$\begingroup\$ Thank you that makes sense, and thanks to JonRB. I sent them an email to see if they can do the via-in-pad and I'll update with their response. \$\endgroup\$ – wdbwbd1 Aug 15 '19 at 0:39

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