0
\$\begingroup\$

I am working on a project involving a source clock with 1MHz frequency. Using a clock divider it is reduced to 4Hz. When I write SDC using the "create_generated_clock -divide_by" command I get an overflow error.

What should I do or what command should I use for this case? I use Cadence® Genus™ Synthesis Solution for synthesis.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.