I'm building an oscillator for a battery powered capacitive position sensor and I need it to have a high swing (>800 mV) at the output while keeping power consumption low enough. I'm feeding the output into the FPGA LVDS input so the oscillator must have a sufficient swing to drive it. Also it has to have large tuning range, a high ΔF/ΔC ratio and one side of the sensor must be grounded.

Right now I'm using a cascode Lampkin oscillator (see picture below), it has quite high sensitivity but it outputs only up to 600 mV into 4 pF load, consuming 2 mA at 3.3V. I recently built a cross-coupled class D oscillator and I got 3 times Vcc at the output while consuming only 1.2 mA! But it's a differential oscillator so I can't use it because the probe is not differential and it can't handle the whole possible capacitance range. I also saw a class-C Hartley oscillator that has higher efficiency by the looks of it but I don't quite understand how it works and how to change the circuit for my application.

So is there any oscillator topologies that are more power efficient than the one I'm using and still sensitive enough to capacitance changes?

enter image description here

  • 1
    \$\begingroup\$ Your schematic looks mighty "Hartley-ish" to me. You'll more-often see two resonating inductors rather than three (L6, L7 with L1=0nH) in a conventional Hartley. Major resonating currents should flow through Cprobe and L1+L6+L7. Your supply is 3.3V? A cascode of 2 DC-coupled transistors leaves little swing for your oscillator voltage. \$\endgroup\$
    – glen_geek
    Aug 15, 2019 at 19:44
  • \$\begingroup\$ What is the capacitance range of your probe? \$\endgroup\$
    – TimWescott
    Aug 15, 2019 at 19:50
  • \$\begingroup\$ @glen_geek well, yes, it's basically Hartley but with an additional inductor for further LC tank decoupling. Drops the swing a little but gives a significant increase in ΔC sensitivity. Yes, my supply is 3.3V but there's also unregulated voltage from a li-ion battery. So there's no benefits from having a cascode in my case? While designing this I was thinking about reducing Miller capacitance so I don't have to build a power hungry CE amplifier. \$\endgroup\$
    – cyrtex
    Aug 15, 2019 at 19:55
  • \$\begingroup\$ @TimWescott 6-18 pF \$\endgroup\$
    – cyrtex
    Aug 15, 2019 at 19:55
  • \$\begingroup\$ Getting power efficiency out of the thing should be more a matter of component choice and biasing -- there's no reason you couldn't bias that thing so that both stages are operating in class C, or close to it. Alternately, you may be able to design the thing to start up quickly, and gate the power to it. If it uses twice the current for 1/10th the time, that's an improvement. \$\endgroup\$
    – TimWescott
    Aug 15, 2019 at 20:07


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