Consider below JK flip flop circuit and truth table:

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I was guessing how Qn+1 column in truth table is calculated.

Interpretation 1

One text book says:

Consider the case J=1, K=0, Qn=0, Qn'=1, line 5 in truth table.

  1. K=0 forces output of G4=1.
  2. All inputs (J, CLK, Qn') of G3 are 1 which makes output of G3 to 0.
  3. G3 output is fed to G1 input. This forces output of G1, Q(n+1) to 1.
  4. This (output of G1) is fed to input of G2 along with output of G4, both of which are 1 (from point 1 and 3). Hence output of G2, Q'(n+1) will be 0.

So in this case output is correctly Q(n+1)=1, Q'(n+1)=0, which is correctly a Set behavior.

Interpretation 2

I was guessing why it doesnt behave like this:

  1. K=0 forces output of G4=1.
  2. Qn=0 which is fed to G2. This forces output of G2, Q'(n+1) to 1.
  3. Q'(n+1)=1 which is fed to G3.
  4. All inputs (J, CLK, Qn') of G3 are 1 which makes output of G3 to 0.
  5. This output of G3 is fed to G1, which forces output of G1, Q(n+1) to 1.

So in this case both Q(n+1) and Q'(n+1) becomes 1, which is invalid.

Why it doesnt behave like interpretation 2 and give invalid state?

  • \$\begingroup\$ In step 2 of interpretation 2 you say that Qn is fed to G3. That's not right, Q'n is fed to G3. \$\endgroup\$ Aug 16, 2019 at 17:43
  • \$\begingroup\$ Yess thats silly mistake, I meant to say G2, but wrote G3. Fixed. The 2nd interpretation still holds correct (as per me), but should have mistake somewhere as the outcome is invalid Q(n+1) = Q'(n+1) = 1. \$\endgroup\$
    – RajS
    Aug 16, 2019 at 19:09

1 Answer 1


You are not done yet.

After Q changes to 1 at step 5 you need to go back to revisit step 2. Q' now becomes 0. This feeds back to G1 and keeps Q at 1.

There are not necessarily just \$n\$ and \$n+1\$ values of the signals. You need to keep propagating the changes through the circuit until no more gate outputs change state. At that point the circuit is stable.

  • \$\begingroup\$ +1 for the last paragraph. Seriously, no text book states that fact. It sounds perfectly logical. Is it obvious one? Because that did not strike in my head. May be am computer science major and not electronics. But I believe books should have stated this clearly for first time reader. \$\endgroup\$
    – RajS
    Aug 17, 2019 at 6:29
  • \$\begingroup\$ That JK flipflop needs to be clocked with a very narrow clock pulse. If the clock pulse is wide then the outputs will oscillate when J=K=1. \$\endgroup\$
    – user173271
    Aug 22, 2019 at 10:45

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