2
\$\begingroup\$

Consider a 2 layer PCB with

  1. Layer 1 is a signal layer (the traces in this layer are indicated with black arrows in the picture below)
  2. Layer 2 is a ground plane, also called GND in the following (the return current path is represented in blue at low frequency, and in green at high frequency).
  3. There are only 2 components: a source ic and a sink ic (target or destination). The common (GND) pin of the sink ic is in the lower left corner.
  4. The signal being sent is a periodic signal.

what is the best way to minimize electromagnetic radiated emissions in this simple case?

My understanding would be that in this simple design, at high frequency, the current will take the path of least inductance (reactance) because the inductive reactance dominates the resistance component of the impedance of the return path. That path will be like the one in green, leading already to a small loop area (indeed the area would be the height between the two layers). To reduce the area further the best option would be to position the two ics as close as possible. Is this correct?

enter image description here

\$\endgroup\$
2
\$\begingroup\$

To reduce the area further the best option would be to position the two ics as close as possible. Is this correct?

Yes.

Other things you can do:

  • If the signal is digital, design the source to have as slow a rising and falling edge speed as possible. This might involve a series resistor at the source's output pin.

  • Add a ground on the top layer, surrounding the signal trace, and connect this to the ground pins of the "source" and "sink" chips. If you're designing controlled impedance traces, you are now working with "coplanar waveguide with ground plane" (sometimes abbreviated "CPWG") rather than microstrip.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.