I'm working on a circuit for control logic. I'm using a 3 bit down counter. There is a control signal that when it goes high starts the counter by presetting it with a value of 5. The counter is clocked off of the inverse of the main clock. I am feeding the 3 bit output into a 3 to 8 decoder. This decoder represents my FSM. The states are as follows: 101 - Initialize: these actions are only done once. States 100 - 001 repeat the same actions the actions are irrelevant here. The final state which is 000 is the stop state. I was successfully able to stop the counter from looping around by sending the inverse signal of the output line from index 0 of the decoder which is state 000 into an and gate along with the inverted clock signal and my start signal. The clock successfully stops. However it kind of put me into a grid lock...
I have another and gate that takes the inverse of the start control line and the 0 index output of the decoder into the reset of the down counter. This does reset the counter but the decoder is still stuck in state 000. There is where I'm stuck. I know why it is happening but I'm not sure how to transition from state 000 back to state 111 after the start line as been toggled from high to low back to high to start it again. When the decoder hits state 0 and that output goes high even if the counter is reset, the inverse line coming from the decoder feeding into the and gate into the counter's clock input that was high before is now low and there is no logic to change it back to high to start the counting process again.
If you need any more information about my circuit don't hesitate to ask and if needs be upon request I can take a screen shot of what I have in Logisim and upload it for a visual aide. However, I think I provided enough information about what I'm trying to accomplish with my counter and FSM, I'm just not sure how to transition out of the Stop - Idle State back to the counting state of the counter.