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I'm working on a circuit for control logic. I'm using a 3 bit down counter. There is a control signal that when it goes high starts the counter by presetting it with a value of 5. The counter is clocked off of the inverse of the main clock. I am feeding the 3 bit output into a 3 to 8 decoder. This decoder represents my FSM. The states are as follows: 101 - Initialize: these actions are only done once. States 100 - 001 repeat the same actions the actions are irrelevant here. The final state which is 000 is the stop state. I was successfully able to stop the counter from looping around by sending the inverse signal of the output line from index 0 of the decoder which is state 000 into an and gate along with the inverted clock signal and my start signal. The clock successfully stops. However it kind of put me into a grid lock...

I have another and gate that takes the inverse of the start control line and the 0 index output of the decoder into the reset of the down counter. This does reset the counter but the decoder is still stuck in state 000. There is where I'm stuck. I know why it is happening but I'm not sure how to transition from state 000 back to state 111 after the start line as been toggled from high to low back to high to start it again. When the decoder hits state 0 and that output goes high even if the counter is reset, the inverse line coming from the decoder feeding into the and gate into the counter's clock input that was high before is now low and there is no logic to change it back to high to start the counting process again.

If you need any more information about my circuit don't hesitate to ask and if needs be upon request I can take a screen shot of what I have in Logisim and upload it for a visual aide. However, I think I provided enough information about what I'm trying to accomplish with my counter and FSM, I'm just not sure how to transition out of the Stop - Idle State back to the counting state of the counter.

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Gating the clock of a synchronous counter is generally a bad idea. It sometimes results in glitches caused by transitions in your decoding logic getting onto the clock line causing unpredictable behavior.

It is better to multiplex a 3 bit signal onto the input the 3 flip flops making up your 3 bit counter. The multiplexers select is your stop signal one input is the normal count input and the other input is the current state.

In the design of synchronous logic we do not think in terms of micromanaging the clock or reset signals, reset is used to set the initial state of the logic at power up. We normally think in terms of controlling the input to, in your case, 3 flip flops. A completed if statement is a multiplexer in RTL in your case your counter input can be described as.

if (initialize=1) then input=5 
  else if (stop =1 ) then input=output
  else input=output-1
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  • \$\begingroup\$ The problem here is that trying the method you described using muxes is that the clock signal is still allowing the counter to count. I need to disable and enable the clock signal between the start control line and the decoder's 0 index out put when the counter reaches 000. \$\endgroup\$ – Francis Cugler Aug 17 '19 at 9:38
  • \$\begingroup\$ The counter will not be counting. You are applying the current state to the input of the 3 Flops making up the counter so it stays the same. I described this badly editing the answer to address. \$\endgroup\$ – RoyC Aug 17 '19 at 9:51
  • \$\begingroup\$ Okay that does make sense; but now it's just the ability to realize that in hardware via logic gates... \$\endgroup\$ – Francis Cugler Aug 17 '19 at 10:29

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