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Let's consider a CMOS inverter. It is known that its propagation delay depends on supply voltage (VDD) and on output parasitic capacitance Cout (which is due both to its transistors' output intrinsic capacitances and to the input capacitances of the cells eventually connected to the output).

But does it depend also on the inverter input capacitance (that is due to its transistors' gate capacitance)?

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  • \$\begingroup\$ The gate-drain overlap capacitance will be a big hog of charge, causing a Miller Plateau. \$\endgroup\$ – analogsystemsrf Aug 17 at 17:42
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The propagation delay depends most significantly on the load capacitance, which is gate capacitance of any transistors that are driven by the output signal as well as the capacitance of the wiring that connects them. As you said, the propagation delay also depends on the power supply voltage.

The propagation delay for an inverter is not really dependent on the input capacitance of that inverter, but it is dependent on the input rise and fall time. Since the input rise and fall time would be dependent on the input capacitance in any real circuit, I guess you could say that the input capacitance of the driving inverter is relevant.

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As follow up to Elliot Alderson where he says: "input capacitance of the driving inverter is relevant."

You find this when adding buffers on an ASIC.

Buffers on an ASIC come in different drive strength: 1x, 2x, 4x, 12x etc. This is achieved by simply putting two or three 1x buffer in parallel. Thus a 4x buffer has four times the driver strength of a 1x buffer, but also four time the input capacitance.

This means that you can make a signal 'slower' if you put a too big buffer in there: the gain at the output can be smaller then the loss at the input.

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