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I've read that for QFN packages at least, the width of the pads on the board should exactly match the width of the feet on the bottom of the chip. However, the datasheet for the part I'm working with (here) shows both typical and maximum sizes for the feet. Which is best to use?
The same question applies for the thermal pad at the center of the chip.
Land pattern recommendations are in the realm of established best practice, rather than definitive proofs. The "same size" recommendation for QFN pads is indeed considered best practice. I'm not sure why, but suspect it has to do with providing a precise locating effect as the solder melts.
So the answer to which to use, typical (nominal) or maximum, is - what does the manufacturer/fab/IPC recommend? At the end of the day it's going to be a tradeoff between thermal performance, locating effect, likelihood of shorts between pads, etc. At 0.1mm, it's not going to be a big effect either way, particularly given board fab tolerances.
I would follow the advice from Freescale Semiconductor in their Application Note AN1902:
The PCB pad width should be approximately the same as the nominal package pad width
That's going to maximise the locating effect and minimise the potential of a short, with a negligible reduction in conductivity/thermal transfer.
