# Eliminating oscillation in a feedback circuit

I have built a switch-mode power supply where the output voltage is controlled by a PWM signal from a microprocessor. The power supply is based on an XL4015. The feedback pin is normally fed by a passive resistor network that sets the output voltage- it's effectively a comparator relative to 1.25V. In this case the feedback pin is connected to the output of an op-amp which compares the output voltage with the filtered PWM voltage.

Vin is the PWM signal, Vout is the output voltage of the SMPSU and Vfb goes to the feedback pin on the XL4015. Unfortunately the circuit oscillates at about 10kHz, presumably because there is no gain-limiting feedback.

The red trace is the feedback signal, and the blue trace is the ripple on the SMPSU output voltage. The steps in the ripple are caused by the 40kHz operating frequency of the SMPSU.

Is there a simple change to this circuit that will make it more stable?

• The circuit has no VISIBLE feedback. Hence, there must be a hidden feedback which causes the problems. By the way: A "gain limiting feedback" always REDUCES the stability properties of an opamp. That is the price we have to pay for a fixed bias point and stable gain values. – LvW Aug 19 '19 at 13:54
• Google difference amplifier and compare with yours. Your is just something that can't work. – Marko Buršič Aug 19 '19 at 14:01
• How clean is the Vcc, does it have the same ripple as the SMPSU, i.e. is Vcc derived from the output of the SMPSU? Is there a decoupling cap close to the opamp? (note the latter question is not the answer to the first) – Huisman Aug 19 '19 at 14:19
• It appears that what you want is for $V_{fb}$ to equal the difference between $V_{out}$ and the average value of $V_{pwm}$ -- is this correct? If so, please edit your question to state that. – TimWescott Aug 19 '19 at 14:46

it's effectively a comparator relative to 1.25V.

It's not a comparator, it's an error amplifier ("EA" on the block diagram). The 33nF cap and the internal series RC are part of the frequency compensation.

It's unclear what kind of voltage range you're trying to achieve. Maybe you want something like Vfb = +1.25V + a*Vout- Vpwm, which would ideally yield an output voltage of Vpwm/a where a < 1.

You could accomplish that with a non-critical op-amp to buffer the filtered PWM and a relatively high bandwidth differential amplifier (two op-amps total). And maybe a reference such as a TLV431 or MCP1501.

If your op-amp has sufficiently high bandwidth compared to the amplifier in the IC, then it might be sufficient stable without adding further compensation components.

Op Amps are high gain with LP compensation at ~ 10 Hz typ. So at 8kHz (your 10kHz est.) 100 to 120 dB gain is reduced by 58~60db but shifted (90 deg lag) and inverted loop input is used for input. But worse yet if the output in any stage stays saturated for too long, that linear gain is now ZERO.
Thus you must make the “error amplifier” have no more than xx=say “10 deg phase shift “ throughout the TBD error loop BW roughly 60 dB down in frequency where you want overall gain 0.1% of output ripple range as your output ripple.

Thus too much gain and zero gain from saturation at some cycle rate becomes a nice Oscillator. Or any lag of feedback or error amplifier saturation or lack of gain margin <0dB at 180 lag or some other method besides Bode Plots means ringing to step loads or oscillation as in your case.

The usual solution is a lead-lag RCR filter just before and after unity loop gain such that your feedback ripple is small but inverted to load-regulated error cycles at desired Loop freq. BW to minimize size of output caps needed with low ESR to buffer step loads outside your error voltage loop delay time (10~90%) =0.35/f(-3dB BW)