# How can I create a long (10 second) pulse from a short active pulse?

So let's say I have an incoming signal: 1 clock cycle from a ~1-100 MHz (50 MHz for this example) clock domain. And I want to drive an output that must be active high for 10 seconds for each time the incoming signal is active high.

There is no check needed for multiple pulse from the input.

My only two ideas is to use multiply clock dividers that will stretch the input pulse.

so x ns active high turns to 2x ns active high, 4x ns, 8x ns.... It will take tons of DFF and inverters.

My second idea, is just toggle the output high, count 10 seconds, and de-assert low. If I have a few 16-bit counters, this should take around 120 DFFs. (50 MHz => 20 ns period) So the incoming active high pulse will trigger the output high and start the counter until it hits >10 seconds (does not have to be accurate).

Which one would be a better implementation (in terms of least DFF used)?

• Now that I think about it, I guess it doesn't matter if I have multiple 16-bit counters. I can just have 1x 114-bit counter.
– Cit5
Aug 19, 2019 at 23:13
• If accuracy is not important why not an analog solution? Aug 19, 2019 at 23:52
• what would you do with a 114 bit timer? ... you said that only one pulse comes in Aug 20, 2019 at 0:02
• @tony a 5ns trigger pulse might be a bit fast for a 555 Aug 20, 2019 at 0:55
• Is there a reason you want a digital (clocked) solution for this, by the way? Aug 20, 2019 at 1:39