So let's say I have an incoming signal: 1 clock cycle from a ~1-100 MHz (50 MHz for this example) clock domain. And I want to drive an output that must be active high for 10 seconds for each time the incoming signal is active high.
There is no check needed for multiple pulse from the input.
My only two ideas is to use multiply clock dividers that will stretch the input pulse.
so x ns active high turns to 2x ns active high, 4x ns, 8x ns.... It will take tons of DFF and inverters.
My second idea, is just toggle the output high, count 10 seconds, and de-assert low. If I have a few 16-bit counters, this should take around 120 DFFs. (50 MHz => 20 ns period) So the incoming active high pulse will trigger the output high and start the counter until it hits >10 seconds (does not have to be accurate).
Which one would be a better implementation (in terms of least DFF used)?