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What does "parasitics extraction" mean in terms of Virtuoso simulation with Calibre?

I know that this simulation is used to have an accurate model of the circuit.

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Everything you create in the IC layout contributes to a parasitic in some form. Each metal wire encounters inductance since current will create a magnetic field, and likewise metals near other metal will create stray capacitances.

Pre-layout simulation cannot account for routing in this way (but it does account for the known capacitances of your FETs and other layout primitives you instantiate). If you have access to Quantus QRC, you can extract parasitics into an av_extracted cellview; open that cellview. You'll get a nice view of the actual results of parasitics extraction.

Additionally, there are layout-dependent effects in the transistors themselves, such as length-of-diffusion effects which increase Id for abutted nMOSFETs while decreasing it for abutted PMOS devices. These can be significant enough that a circuit can meet spec in simulation, and then completely fail in layout.

As a particular example, I had a folded cascode with extremely tight current tolerances that I laid out with abutted current mirrors; when I extracted the parasitics the current mirrors' current had changed so much that the output branch of the cascode received zero current and my amplifier failed to, well, amplify.

Before layout, there was absolutely no way to know of this failure in a simulator -- the simulator could not have predicted my intent to lay out my circuit in this way, and the most straightforward layout without transistor abutment would not have had the same issue.

Observe, in the below figure, the green parasitic elements (some of which are freehand circled). These represent important parasitics that my PDK supported, such as contact/via resistance, inter-layer capacitance, wire resistance (especially important for poly), etc. Click on the image to see it at 1:1 scale.

A Cadence Virtuoso av_extracted cellview showing parasitic resistances and capacitances associated with layout elements

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  • \$\begingroup\$ " I had a folded cascode with extremely tight current tolerances that I laid out with abutted current mirrors; when I extracted the parasitics the current mirrors' current had changed so much that the output branch of the cascode received zero current and my amplifier failed to, well, amplify." I wonder what technology node this was? I'm not experiencing this at 55nm maybe my transistor are too big to experience this. \$\endgroup\$
    – user132893
    Nov 9, 2023 at 18:39
  • \$\begingroup\$ @onepound I was on 180nm, with very aggressive abutment and a very skewed intended ratio between the transconductor and the load sides (which I then learned was hard to pull off). I wouldn't expect this at a more sensible 1:1 or 3:1 or similar current ratio \$\endgroup\$
    – nanofarad
    Nov 9, 2023 at 19:43
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Every conducting structure on an integrated circuit has capacitance, resistance, and inductance. You usually didn't ask for a capacitor or a resistor or an inductor, but they are present inherently. To perform an accurate simulation you must include the effects of these parasitic elements. The process of parasitic extraction is the estimation of these element values using a 3-dimensional model of your circuit.

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  • \$\begingroup\$ How can I link this with IC Layout? Is it the routing and the changing in layers(vias) that adds those parasitics compared to the schematics simulation? \$\endgroup\$
    – tairit
    Aug 20, 2019 at 12:33
  • \$\begingroup\$ Yes, the parasitics are due to the physical layout, including the routing of signals. But you can also extract parasitics from structures like transistor gates and implanted regions. \$\endgroup\$ Aug 20, 2019 at 14:57

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