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I know following variants of SR flip flop:

  1. Using NAND-NAND combination

    enter image description here enter image description here

  2. Using AND-NOR combination

    enter image description here enter image description here

I was guessing how we can obtain JK flip flop for each of these variants. I found below approach showing how we can convert NAND-NAND SR flip flop in JK flip flop: enter image description here

So, by above approach, we are getting,

S = J'Q and R = KQ

However I did not find any text / website explaining how to convert AND-NOR SR flip flop to JK flip flop. So I tried myself as follows:

enter image description here

By above approach, we are getting

S=J'+KQ' and R=K'+Q'

I searched online for correctness of this. Didnt found anything. Only found this page which shows JK flip flip using NOR-NOR gates as follows:

enter image description here

This flip flop comes with KQ and JQ' which definitely does not match with what I have got.

Can someone tell, if I was correct with S=J'+KQ' and R=K'+Q' or I was wrong and the above diagram is correct?

Edit

After some more thinking, I feel I got it. As we have two implementations of SR flip flop, we are supposed to have two implementations of JK flip flop: 1st implementation replacing forbidden state in NAND-NAND SR flip flop with toggle state and 2nd implementation replacing forbidden state in AND-NOR SR flip flop with toggle state. What I was trying to do is using AND-NOR SR flip flop to prepare 1st implementation of JK flip flop!!! If I try to prepare 2nd implementation of JK flip flop with AND-NOR SR flip flop, I get something as follows:

enter image description here

The outcome looks more reasonable. I am getting S=J+Q and R=Q'+K unlike S=J'+KQ' and R=K'+Q' I earlier obtained. Do you feel this correct? I believe last image before edit is anyway incorrect, right?

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  • \$\begingroup\$ You could use next to any digital simulator to check your solution. From personal experience I can recommend Logisim. \$\endgroup\$ – the busybee Aug 20 at 20:23
  • \$\begingroup\$ I dont get what I have to check by simulating here. I want to know if the version of JK flip flop I have come up with with different variations of SR are valid or not. How a simulation can tell if the circuit is a valid JK flip flop because I dont know if the output behavior itself is acceptable as JK flip flop output. Will need someone with knowledge to confirm. \$\endgroup\$ – anir Aug 22 at 6:25
  • \$\begingroup\$ Because you asked "Can someone tell, if I was correct..." you could compare against a readily provided JK flip flop. \$\endgroup\$ – the busybee Aug 22 at 6:42
  • \$\begingroup\$ But the way some sources provide two variations (NAND NAND and AND NOR) of SR flip flop, I found no text / website providing corresponding two variations of JK flip flop. All provide same JK flip flop obtained from NAND-NAND SR flip flop. I feel it will be wrong if I compare truth table of JK flip flop obtained from NAND NAND SR flip flop with truth table of JK flip flop obtained from AND NOR SR flip flop. \$\endgroup\$ – anir Aug 22 at 7:16
  • \$\begingroup\$ But, doesn't behave JK flip flops equally, independent from their inner composition of NAND NAND FF or AND NOR FF? So, if your logic is correct, it behaves as any other JK flip flop. Or do we have a misunderstanding concerning "flip flop" (which is edge-triggered) and "latch" (which is level-triggered)? \$\endgroup\$ – the busybee Aug 22 at 9:38
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First part of an answer, there are still open ends...


Found by experimenting with the mentioned logic simulator, but can be obtained by thinking, too.

The table of the AND NOR flip flop seems wrong to me.

  1. When both S and R are 0 it's the same case as when CLK is 0 due to the ANDs. Therefore it can't be forbidden.
  2. There is a forbidden state change if S and R are both 1 and CLK changes from 1 to 0. The circuit starts to oscillate, therefore this must be forbidden. This is the same as for the other flip flop.

It should be equal to the table of the NAND NAND flip flop concerning the actions. But when both S and R are 1 and CLK is 1, the flip flops produce different values. The NAND NAND FF sets both Q and Q' on 1, the AND NOR FF sets both on 0.

You can use transformations from NAND to NOR to see why this has to be like this.


Using a pulse detector is a difficult thing, not to say dangerous. You can't be sure that the generated pulse is wide enough to meet the setup conditions for the following gates.

As I learned edge-triggered flip flops in the real world are built from two level-triggered flip flops with complementary level sensitivity. This is called "master-slave".


Lesson learned: Not every web site that looks instructive fulfils its promises.

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  • \$\begingroup\$ The truth tables for the two RS flipflops should be identical assuming you keep the input labels to the two circuits as they are. The Nand/Nand table is correct as it is. \$\endgroup\$ – James Aug 22 at 13:03
  • \$\begingroup\$ @James Thanks! That's right for "set" and "reset", I'll edit my answer. But for both on 1 both flip flops output different values. \$\endgroup\$ – the busybee Aug 22 at 13:12
  • \$\begingroup\$ @busybee Yes agreed. Forbidden input state for both RS flipflops is with both inputs high. For Nand/Nand both inputs high gives both outputs high. For And/Nor both inputs high gives both outputs low. Got there in the end! Too late to edit my comment. \$\endgroup\$ – James Aug 22 at 13:27

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