Different implementations of JK flip flop

Question

I know following variants of SR flip flop:

1. Using NAND-NAND combination

   

2. Using AND-NOR combination

   

I was guessing how we can obtain JK flip flop for each of these variants. I found below approach showing how we can convert NAND-NAND SR flip flop in JK flip flop:

So, by above approach, we are getting,

S = J'Q and R = KQ

However I did not find any text / website explaining how to convert AND-NOR SR flip flop to JK flip flop. So I tried myself as follows:

By above approach, we are getting

S=J'+KQ' and R=K'+Q'

I searched online for correctness of this. Didnt found anything. Only found this page which shows JK flip flip using NOR-NOR gates as follows:

This flip flop comes with KQ and JQ' which definitely does not match with what I have got.

Can someone tell, if I was correct with S=J'+KQ' and R=K'+Q' or I was wrong and the above diagram is correct?

Edit

After some more thinking, I feel I got it. As we have two implementations of SR flip flop, we are supposed to have two implementations of JK flip flop: 1st implementation replacing forbidden state in NAND-NAND SR flip flop with toggle state and 2nd implementation replacing forbidden state in AND-NOR SR flip flop with toggle state. What I was trying to do is using AND-NOR SR flip flop to prepare 1st implementation of JK flip flop!!! If I try to prepare 2nd implementation of JK flip flop with AND-NOR SR flip flop, I get something as follows:

The outcome looks more reasonable. I am getting S=J+Q and R=Q'+K unlike S=J'+KQ' and R=K'+Q' I earlier obtained. Do you feel this correct? I believe last image before edit is anyway incorrect, right?

Answer 1

First part of an answer, there are still open ends...

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Found by experimenting with the mentioned logic simulator, but can be obtained by thinking, too.

The table of the AND NOR flip flop seems wrong to me.

1. When both S and R are 0 it's the same case as when CLK is 0 due to the ANDs. Therefore it can't be forbidden.
2. There is a forbidden state change if S and R are both 1 and CLK changes from 1 to 0. The circuit starts to oscillate, therefore this must be forbidden. This is the same as for the other flip flop.

It should be equal to the table of the NAND NAND flip flop concerning the actions. But when both S and R are 1 and CLK is 1, the flip flops produce different values. The NAND NAND FF sets both Q and Q' on 1, the AND NOR FF sets both on 0.

You can use transformations from NAND to NOR to see why this has to be like this.

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Using a pulse detector is a difficult thing, not to say dangerous. You can't be sure that the generated pulse is wide enough to meet the setup conditions for the following gates.

As I learned edge-triggered flip flops in the real world are built from two level-triggered flip flops with complementary level sensitivity. This is called "master-slave".

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Lesson learned: Not every web site that looks instructive fulfils its promises.