I'm a bit of a newbie with FPGAs.

Trying to run the project from the "Getting Started" section of the Lattice Diamond manual.

These are the source files:


module count(c_up,c_down,clk,rst,c_up_2,c_down_2,c_down_3);

input clk,rst;
output [2:0]c_up;
output [2:0]c_down;
output [2:0]c_up_2;
output [2:0]c_down_2;
output [2:0]c_down_3;

count_up count_up_inst (.clk(clk), .rst(rst), .c_up(c_up));
count_down count_down_inst (.clk(clk), .rst(rst), .c_down(c_down));
count_up_2 count_up_2_inst (.clk(clk), .rst(rst), .c_up(c_up_2));
count_down_2 count_down_2_inst (.clk(clk), .rst(rst), .c_down(c_down_2));
count_down_3 count_down_3_inst (.clk(clk), .rst(rst), .c_down(c_down_3));




module count_down (clk,rst,c_down)/* synthesis GSR="DISABLED" */;
input clk, rst;
output [2:0]c_down;

reg [2:0]c_down;

always @(posedge clk or posedge rst)
        if (rst)
           c_down = 3'b111;
           c_down = c_down - 1;


module count_up (clk,rst,c_up)/* synthesis GSR="ENABLED" */;

(the rest is essentially the same, just on reset init to 000, 
and on clk's posedge increase instead of decrease)

There's also count_down_2.v and count_up_2.v that do the same, increasing or decreasing in steps of 2. And there is a count_down_3.vhd that seems to do the same, just in steps of 3 when counting down.

The synthesis goes well all the way to generation of the JDEC file. I'm using the TinyFPGA programmer software, and that one reports erasing, flashing, and verifying all OK.

However, the pins of the TinyFPGA board don't move at all. The red LED is on (if I'm understanding correctly, that's just an indicator that the board has the 3.3V power in). Pins 12, 13, 14, 15 show a 1011 output, and most other pins are at 0.

Aside from the obvious question of why is it not working, I have a couple of concrete questions:

  • How do I specify the mapping of the pins? (i.e., output signals/variables in the Verilog code corresponding to specific pins on the chip) I can't seem to find any such definition anywhere in the project. I know I specified the correct chip (LCMXO2-1200HC-4SG32C); even if the application just knows the mapping, how do I know the names I need to use to output to or input from a given pin in the chip?
  • Do I need to set up the clock? (I guess maybe the chip internally generates a clock with default characteristics --- but I'm not sure whether that's the case, and whether that's what I'm missing?)


  • 3
    \$\begingroup\$ The "getting started" of the Diamond is maybe not the best choice as it is intended for the starter kits from lattice (which are actually not that expensive considering the components and capabilities). Have a look at tinyfpga.com/a-series-guide.html which gives you a starting point for the tiny module. Especially it demonstrates the use of the internal oscillator as clock source and include correct pin mapping files. \$\endgroup\$ Commented Aug 21, 2019 at 23:48
  • \$\begingroup\$ aarrrghh!!! Could not agree more, Christian B. After figuring out the issue (demo is now working), I'm so furious that Lattice would provide such a poor and absoloutely-non-informative/non-helpful demo to get their users started!!!! :-( \$\endgroup\$
    – Cal-linux
    Commented Aug 22, 2019 at 2:24
  • 2
    \$\begingroup\$ Well the demo provided by lattice semi works just fine if used with the correspondening hardware/board ;) but glad to hear you found a solution. \$\endgroup\$ Commented Aug 22, 2019 at 7:03
  • \$\begingroup\$ "works just fine if used with the corresponding hardware/board" --- I actually had thought of that; but I don't understand how it can work; it does not instantiate a clock, and it does not have any pin assignments (is it perhaps that the Latt Diamond is "smart" and when it sees a different hardware, then it omits the parts that are specific to the intended demo hardware?) \$\endgroup\$
    – Cal-linux
    Commented Aug 22, 2019 at 11:34
  • \$\begingroup\$ At least the Machxo2 breakout board guide explains how to find MachXO21200ZEBreakoutBoardDemoDesignSource.zip which has a pin assignment file included. The clock is typically sourced from the FT crystal which is on the one hand smart and on the other very dumb. Cus if one accidentally forgets to assign a clock output and the pin is free the diamond will likely assign the output to it which implies that the crystal cannot start correctly anymore. \$\endgroup\$ Commented Aug 22, 2019 at 13:02

1 Answer 1


Here is another answer on StackExchange which explains pin assignment for Lattice devices: https://electronics.stackexchange.com/a/232013/213609

As a starting point, I'd suggest you just synthesize some super-primitive combinatorial logic like a NOT gate or even just fixed '0' and '1' values so you can prove to yourself that you're getting the pin assignments correct. Once that's working, then move on to the counter with its CLK and RST signals.

  • \$\begingroup\$ Thanks for that link --- that answer in turn posts a link to a Youtube video, and in that video (which is for the Lattice MachXO2 Breakout dev board), the guy explains nicely and perfectly. Turns out, the MachXO2 does have an internal RC oscillator (low-precision in the frequency, but perfectly good for a "getting started" counter demo. As mentioned in my other comment, the demo is now working, and I see the square waves at the correct frequencies on the selected pins! (yay!) \$\endgroup\$
    – Cal-linux
    Commented Aug 22, 2019 at 2:27
  • \$\begingroup\$ Glad I could help, but d'oh, I was wrong about the clock. I will edit to fix that; I can't stand the thought of spreading misinformation. \$\endgroup\$
    – Mr. Snrub
    Commented Aug 22, 2019 at 5:11
  • \$\begingroup\$ I actually would have preferred that you left that detail about the clock --- your comment that the logic by itself will sit and do nothing unless a clock is present, that is correct and I think it's helpful for someone else in the future stumbling into this post (it was indeed helpful for me!). The part that you mentioned that I needed a signal generator to inject a clock, that would be the only part that you needed to remove. \$\endgroup\$
    – Cal-linux
    Commented Aug 22, 2019 at 11:38

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